公开(公告)号：US06725407B2

公开(公告)日：2004-04-20

申请号：US10105591

申请日：2002-03-25

申请人： Michael Richter ,  Jan Otterstedt

发明人： Michael Richter ,  Jan Otterstedt

IPC分类号： G01R3128

CPC分类号： G01R31/31719 ,  G01R31/318533

摘要： The invention relates to a method for protecting data during a self-test of a microcontrollers, in which all of the circuit elements within the microcontroller can be tested, where the course of the self-test cannot be altered via the external pins, and no intermediate results are passed to the outside via the pins. The invention also relates to an configuration in the form of an integrated circuit which can be used to implement the method, and to correspondingly equipped microcontrollers.

摘要翻译： 本发明涉及一种用于在微控制器的自检期间保护数据的方法，其中可以测试微控制器内的所有电路元件，其中自检过程不能通过外部引脚改变，而无 中间结果通过引脚传递到外部。 本发明还涉及可用于实现该方法的集成电路形式的配置以及相应地配备的微控制器。

公开(公告)号：US06496119B1

公开(公告)日：2002-12-17

申请号：US09582841

申请日：2000-09-20

申请人： Jan Otterstedt ,  Michael Richter ,  Michael Smola ,  Martin Eisele

发明人： Jan Otterstedt ,  Michael Richter ,  Michael Smola ,  Martin Eisele

IPC分类号： G08B2100

CPC分类号： G06K19/073 ,  G01R31/31719 ,  G06F21/71 ,  G06F21/74 ,  G06F21/87 ,  G06F2221/2105 ,  G06F2221/2143 ,  G06K19/07372 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention is directed to a protective circuit for an integrated circuit 1. This protective circuit is preferably arranged in a plurality of circuit levels 2, 3 under and/or above the intergrated circuit 1. It exhibits a plurality of interconnects 10, 11 that are charged with different signals of one or more signal generators. The different signals, after traversing the interconnects 10, 11, are analyzed with one or more detectors in that the signals received by detectors are respectively compared to rated reference signals, and an alarm signal is forwarded to the integrated circuit given the presence of a significant difference. On the basis of this alarm signal, the integrated circuit is switched into a security mode that makes an analysis or a manipulation of the integrated circuit practically impossible.

摘要翻译： 本发明涉及用于集成电路1的保护电路。该保护电路优选地布置在集成电路1下面和/或上方的多个电路级2,3中。它呈现多个互连10,11 充电一个或多个信号发生器的不同信号。 通过一个或多个检测器分析遍历互连10,11之后的不同信号，因为由检测器接收的信号分别与额定参考信号进行比较，并且在存在显着的信号的情况下将报警信号转发到集成电路 区别。 基于该报警信号，集成电路切换成能够实现集成电路的分析或操作的安全模式。

公开(公告)号：US08837210B2

公开(公告)日：2014-09-16

申请号：US13592404

申请日：2012-08-23

申请人： Mihail Jefremow ,  Wolf Allers ,  Jan Otterstedt ,  Christian Peters ,  Thomas Kern

发明人： Mihail Jefremow ,  Wolf Allers ,  Jan Otterstedt ,  Christian Peters ,  Thomas Kern

IPC分类号： G11C11/00

CPC分类号： G11C29/028 ,  G11C11/16 ,  G11C11/1673 ,  G11C29/021 ,  G11C2029/5006

摘要： The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a system for reading a memory cell includes a read path and a precharge path. The reference current is provided through the read path and is sampled via a sampling element in the read path. Subsequently, a current from the memory cell is provided through the same sampling element and read path. The output level is then determined by the cell current working against the sampled reference current.

摘要翻译： 本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。 根据本发明的一个方面，用于读取存储单元的系统包括读取通道和预充电路径。 参考电流通过读取路径提供，并通过读取路径中的采样元件进行采样。 随后，通过相同的采样元件和读取路径提供来自存储单元的电流。 然后，输出电平由针对采样参考电流工作的电池电流确定。

公开(公告)号：US08437175B2

公开(公告)日：2013-05-07

申请号：US13408389

申请日：2012-02-29

申请人： Thomas Nirschl ,  Jan Otterstedt ,  Michael Bollu ,  Wolf Allers

发明人： Thomas Nirschl ,  Jan Otterstedt ,  Michael Bollu ,  Wolf Allers

IPC分类号： G11C11/24

CPC分类号： G11C16/12 ,  G11C16/24

摘要： In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.

摘要翻译： 在一个实施例中，公开了位线接口。 位线接口具有多路复用器，其具有多个位线输出，以及耦合到多路复用器信号输入的写入路径。 位线接口还具有耦合到多路复用器信号输入的读取路径，其中读取路径和写入路径共享至少一个组件。

公开(公告)号：US08327062B2

公开(公告)日：2012-12-04

申请号：US12331206

申请日：2008-12-09

申请人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

发明人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

IPC分类号： G06F12/00 ,  G06F12/04 ,  G06F12/06 ,  G06F13/00 ,  G11C16/02 ,  G11C16/16

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C13/0069 ,  G11C2013/0088

摘要： Non volatile memories and methods of programming thereof are disclosed. In one embodiment, the method of programming a memory array includes receiving a series of data blocks, each data block having a number of bits that are to be programmed, determining the number of bits that are to be programmed in a first data block, determining the number of bits that are to be programmed in a second data block, and writing the first data block and the second data block into the memory array in parallel if the sum of the number of bits that are to be programmed in the first data block and the second data block is not greater than a maximum value. The first and second data blocks may or may not be adjacent data blocks. Improved programming efficiency may be achieved in a memory circuit when the maximum allowable current may be limited by the application or the size of a charge pump. Inverse data may be written in parallel if the sum is greater than the maximum value.

摘要翻译： 公开了非易失性存储器及其编程方法。 在一个实施例中，编程存储器阵列的方法包括接收一系列数据块，每个数据块具有要被编程的位数，确定要在第一数据块中编程的位的数量，确定 要在第二数据块中编程的比特数，以及如果要在第一数据块中编程的比特数的总和，并行地将第一数据块和第二数据块并入到存储器阵列中 并且第二数据块不大于最大值。 第一和第二数据块可以是或可以不是相邻的数据块。 当最大允许电流受应用或电荷泵的尺寸限制时，可在存储器电路中实现改进的编程效率。 如果和大于最大值，反数据可以并行写入。

公开(公告)号：US08243520B2

公开(公告)日：2012-08-14

申请号：US12610781

申请日：2009-11-02

申请人： Nigel Chan ,  Wolf Allers ,  Michael Bollu ,  Dimitri Lebedev ,  Jan Otterstedt ,  Christian Peters

发明人： Nigel Chan ,  Wolf Allers ,  Michael Bollu ,  Dimitri Lebedev ,  Jan Otterstedt ,  Christian Peters

IPC分类号： G11C11/34

CPC分类号： G11C16/349 ,  G11C16/0483 ,  G11C16/06

摘要： A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse parameters each having a fixed valued, and determining a fail count by measuring the number of non-volatile memory cells of the plurality of non-volatile memory cells having a storage parameter level exceeding a verify level. The method further includes determining a change in an programming behavior of the plurality of non-volatile memory cells based on the fail count, adjusting a value of at least one pulse parameter of at least one second programming pulse defined by the plurality of pulse parameters to a desired value based on the change in programming behavior, and applying the at least one second programming pulse to the plurality non-volatile memory cells.

摘要翻译： 操作集成电路的方法包括将至少一个第一编程脉冲施加到多个非易失性存储器单元以调整每个非易失性存储单元的存储参数的电平，所述至少一个第一编程脉冲被定义 通过多个具有固定值的脉冲参数，并且通过测量具有超过验证电平的存储参数电平的多个非易失性存储器单元的非易失性存储器单元的数量来确定故障计数。 该方法还包括基于故障计数确定多个非易失性存储器单元的编程行为的变化，将由多个脉冲参数定义的至少一个第二编程脉冲的至少一个脉冲参数的值调整为 基于编程行为的变化的期望值，以及将所述至少一个第二编程脉冲应用于所述多个非易失性存储器单元。

公开(公告)号：US20100065891A1

公开(公告)日：2010-03-18

申请号：US12212097

申请日：2008-09-17

申请人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

发明人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

IPC分类号： H01L23/52

CPC分类号： H01L23/52 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

摘要翻译： 本发明的实施例描述了紧凑型存储器阵列。 在一个实施例中，存储单元阵列包括设置在衬底上的第一，第二和第三栅极线，第二栅极线设置在第一和第三栅极线之间。 第一，第二和第三栅极线形成存储单元阵列的相邻栅极线。 存储单元阵列还包括布置在第一栅极线上的第一金属线，耦合到第一栅极线的第一金属线; 第二金属线设置在第二栅极线上，第二金属线耦合到第二栅极线; 以及设置在所述第三栅极线上的第三金属线，所述第三金属线耦合到所述第三栅极线。 第一金属线，第二金属线和第三金属线设置在不同的金属化水平。

公开(公告)号：US07580297B2

公开(公告)日：2009-08-25

申请号：US11731766

申请日：2007-03-30

申请人： Thomas Nirschl ,  Jan Otterstedt

发明人： Thomas Nirschl ,  Jan Otterstedt

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

摘要： A multi-level sensing scheme compares the state of a multi-level storage cell with monotonously changing reference states, which are associated to different information values. That particular information value is identified to be the information stored in the multi-level storage cell, which has associated that reference state which, in a changing direction, firstly exceeds the state.

摘要翻译： 多级感测方案将多级存储单元的状态与单调变化的参考状态进行比较，其与不同的信息值相关联。 该特定信息值被识别为存储在多级存储单元中的信息，其与改变方向上首先超过该状态的参考状态相关联。

公开(公告)号：US20080298121A1

公开(公告)日：2008-12-04

申请号：US11756639

申请日：2007-06-01

申请人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

发明人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/79

摘要： A method of operating a phase-change memory array. The method may comprise causing a first current to flow through a phase-change memory element in a first direction and causing a second current to flow through the memory element in a second direction.

摘要翻译： 一种操作相变存储器阵列的方法。 该方法可以包括使第一电流在第一方向上流过相变存储元件，并使第二电流沿第二方向流过存储元件。

公开(公告)号：US09251864B2

公开(公告)日：2016-02-02

申请号：US13605129

申请日：2012-09-06

申请人： Jan Otterstedt ,  Wolf Allers ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro ,  Thomas Kern

发明人： Jan Otterstedt ,  Wolf Allers ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro ,  Thomas Kern

IPC分类号： G11C29/04 ,  G11C29/02 ,  G11C5/14

CPC分类号： G11C29/83 ,  G11C5/143 ,  G11C29/02 ,  G11C29/04 ,  G11C29/832

摘要： The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.

摘要翻译： 本发明涉及一种电子存储器系统，更具体地说，涉及一种用于在存储器件中提供电压保护的系统，以及一种在存储器件中提供电压保护的方法。 根据实施例，提供了一种用于在存储器件中提供电压保护的系统，该系统包括一个存储器阵列，该存储器阵列包括布置在多组存储器单元中的多个存储单元，以及多个限流元件，其中 每组存储器单元与至少一个限流元件相关联。