公开(公告)号：US06614119B1

公开(公告)日：2003-09-02

申请号：US09521771

申请日：2000-03-09

申请人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

发明人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

IPC分类号： H01L2940

CPC分类号： H01L21/76814 ,  H01L21/28518 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76877

摘要： A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300° C. to 550° C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.; (e) a step of forming a first aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the wetting layer at a temperature of no more than 200° C.; and (f) a step of forming a second aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the first aluminum layer at a temperature of at least 300° C.

摘要翻译： 一种具有接触结构的半导体器件，其可以显示出最高级的覆盖范围，而不引起空隙或接线不连续性，使用铝或铝合金作为通孔的导电物质。 制造半导体器件的方法包括：对于在半导体衬底上的第一布线区域上方的布线区域中的至少一层的以下步骤（a）至（f）：（a）形成通孔的步骤 形成在半导体衬底上的第一布线区域上方的第二层间电介质; （b）通过减压热处理和基板温度在300℃至550℃下除去层间电介质中包含的气体组分的脱气步骤; （c）在层间电介质和通孔的表面上形成润湿层的步骤; （d）将基板冷却至不超过100℃的温度; （e）在不超过200℃的温度下形成包含铝和合金中的铝的第一铝层的步骤，其中铝是润湿层上的主要成分; 以及（f）在至少300℃的温度下形成第一铝层的步骤，所述第二铝层包括铝和合金之一，其中铝是第一铝层上的主要成分。

公开(公告)号：US6144097A

公开(公告)日：2000-11-07

申请号：US220590

申请日：1998-12-28

申请人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

发明人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/927

摘要： A semiconductor device comprising a semiconductor substrate including an electronic element, interlayer dielectric (silicon oxide layer and BPSG layer) formed on the semiconductor substrate, a contact hole formed in the interlayer dielectric, a barrier layer formed on the interlayer dielectric and contact hole, and a wiring layer formed on the barrier layer. In the barrier layer, metal oxide (titanium oxide) are scattered in an island-like configuration. The barrier layer is formed by depositing a layer that is used to form the barrier layer and then introducing oxygen into the layer. The step is achieved by depositing a layer for the barrier layer, exposing the layer in oxygen plasma under reduced pressure, and subjecting the layer to the thermal processing, or, alternatively by depositing a layer for the barrier layer and subjecting the layer to thermal processing in an atmosphere of oxygen. The semiconductor device of the present invention has a barrier layer with excellent barrier properties.

摘要翻译： 一种半导体器件，包括形成在半导体衬底上的电子元件，层间电介质（氧化硅层和BPSG层）的半导体衬底，形成在层间电介质中的接触孔，形成在层间电介质和接触孔上的阻挡层，以及 形成在阻挡层上的布线层。 在阻挡层中，金属氧化物（氧化钛）以岛状构造分散。 阻挡层通过沉积用于形成阻挡层然后将氧引入层中的层而形成。 该步骤通过沉积阻挡层的层，在减压下在氧等离子体中暴露层，并对该层进行热处理，或者通过沉积用于阻挡层的层并使该层进行热处理来实现 在氧气氛中。 本发明的半导体装置具有阻隔性优异的阻挡层。

公开(公告)号：US06107182A

公开(公告)日：2000-08-22

申请号：US161920

申请日：1998-09-29

申请人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

发明人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

IPC分类号： H01L21/203 ,  H01L21/285 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76814 ,  H01L21/28518 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76877

摘要： A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300.degree. C. to 550.degree. C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100.degree. C.; (e) a step of forming a first aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the wetting layer at a temperature of no more than 200.degree. C.; and (f) a step of forming a second aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the first aluminum layer at a temperature of at least 300.degree. C.

摘要翻译： 一种具有接触结构的半导体器件，其可以显示出最高级的覆盖范围，而不引起空隙或接线不连续性，使用铝或铝合金作为通孔的导电物质。 制造半导体器件的方法包括：对于在半导体衬底上的第一布线区域上方的至少一层布线区域，以下步骤（a）至（f）：（a）形成通孔的步骤 形成在半导体衬底上的第一布线区域上方的第二层间电介质; （b）通过减压热处理和基板温度在300℃至550℃除去层间电介质中包含的气体组分的脱气步骤。 （c）在层间电介质和通孔的表面上形成润湿层的步骤; （d）将基板冷却至不超过100℃的温度; （e）在不超过200℃的温度下形成包含铝和合金中的铝的第一铝层的步骤，其中铝是润湿层上的主要成分。 和（f）在至少300℃的温度下形成第一铝层的步骤，所述第二铝层包括铝和合金中的一种，其中铝是第一铝层上的主要成分。

公开(公告)号：US06486555B2

公开(公告)日：2002-11-26

申请号：US09140016

申请日：1998-08-26

申请人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

发明人： Michio Asahina ,  Junichi Takeuchi ,  Naohiro Moriya ,  Kazuki Matsumoto

IPC分类号： H01L2348

CPC分类号： H01L21/76856 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device comprises the following steps (a) to (f): (a) a step of forming a the contact hole in an interlayer dielectric formed on a semiconductor substrate including an electronic element; (b) a degassing step for removing gaseous components included within the interlayer dielectric, by thermal processing under a reduced pressure at a substrate temperature of 300° C. to 550° C.; (c) a step of forming a barrier layer on the interlayer dielectric and the contact hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.; (e) a step of forming a first aluminum layer on the barrier layer, at a temperature of no more than 200° C., including aluminum or an alloy in which aluminum is the main component; and (f) a step is of forming a second aluminum layer on the first aluminum layer, at a temperature of at least 300° C., including aluminum or an alloy in which aluminum is the main component.

摘要翻译： 一种制造半导体器件的方法包括以下步骤（a）至（f）：（a）在包括电子元件的半导体衬底上形成的层间电介质中形成接触孔的步骤; （b）通过在300℃至550℃的基板温度下在减压下热处理来去除包含在层间电介质中的气体组分的脱气步骤。 （c）在所述层间电介质和所述接触孔上形成阻挡层的步骤; （d）将基板冷却至不超过100℃的温度; （e）在不超过200℃的温度下在阻挡层上形成第一铝层的步骤，包括铝或以铝为主要成分的合金; 和（f）步骤是在至少300℃的温度下在第一铝层上形成第二铝层，包括铝或其中以铝为主要成分的合金。

公开(公告)号：US06458703B2

公开(公告)日：2002-10-01

申请号：US09389515

申请日：1999-09-03

申请人： Mamoru Endo ,  Junichi Takeuchi ,  Michio Asahina ,  Eiji Suzuki ,  Kazuki Matsumoto

发明人： Mamoru Endo ,  Junichi Takeuchi ,  Michio Asahina ,  Eiji Suzuki ,  Kazuki Matsumoto

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76877

摘要： A method for manufacturing a semiconductor device that fills contact holes with conductive material such as aluminum or an aluminum alloy. A semiconductor device is manufactured by the process of forming an opening such as a contact hole in an interlayer dielectric film formed on a semiconductor substrate having a device element formed thereon. A first film and a second film made of conductive material such as aluminum or an alloy containing aluminum are formed on the interlayer dielectric film and the opening. The second film is then gradually cooled.

摘要翻译： 一种半导体器件的制造方法，其用诸如铝或铝合金的导电材料填充接触孔。 通过在其上形成有器件元件的半导体衬底上形成的层间电介质膜中形成诸如接触孔的开口的方法来制造半导体器件。 在层间电介质膜和开口上形成由铝或含有铝的合金的导电材料制成的第一膜和第二膜。 然后第二个膜逐渐冷却。

公开(公告)号：US08679360B2

公开(公告)日：2014-03-25

申请号：US13432680

申请日：2012-03-28

申请人： Takeshi Sakamoto ,  Junichi Takeuchi

发明人： Takeshi Sakamoto ,  Junichi Takeuchi

IPC分类号： B44C1/22 ,  H01L21/302

CPC分类号： H01L21/304 ,  B81C1/00063 ,  B81C2201/053

摘要： A base surface processing method includes forming a protective film on a base surface; thinning a part of a base by grinding a part of the base surface; and etching a ground surface ground by the thinning.

摘要翻译： 基面处理方法包括在基面上形成保护膜; 通过研磨基底表面的一部分来减薄基底的一部分; 并通过变薄来蚀刻地面。

公开(公告)号：US08039976B2

公开(公告)日：2011-10-18

申请号：US12310128

申请日：2007-07-11

申请人： Eiji Sato ,  Ryoji Oki ,  Junichi Takeuchi

发明人： Eiji Sato ,  Ryoji Oki ,  Junichi Takeuchi

IPC分类号： H02P9/04

CPC分类号： B60W20/10 ,  B60K6/28 ,  B60K6/48 ,  B60K6/547 ,  B60L3/0046 ,  B60L11/14 ,  B60L11/1868 ,  B60L11/187 ,  B60L11/1872 ,  B60L2210/10 ,  B60L2210/40 ,  B60L2240/445 ,  B60L2270/20 ,  B60W10/06 ,  B60W10/08 ,  B60W10/24 ,  B60W10/26 ,  B60W10/30 ,  B60W20/00 ,  B60W30/194 ,  B60W2510/0676 ,  B60W2510/244 ,  B60W2510/246 ,  B60Y2400/112 ,  F02D29/02 ,  F02D29/06 ,  F02D2200/503 ,  F02N11/04 ,  F02N11/0848 ,  F02N11/0866 ,  F02N2011/0888 ,  F02N2011/0896 ,  F02N2200/023 ,  F02N2200/046 ,  F02N2200/064 ,  Y02T10/6221 ,  Y02T10/6278 ,  Y02T10/6286 ,  Y02T10/70 ,  Y02T10/7005 ,  Y02T10/7066 ,  Y02T10/7077 ,  Y02T10/7216 ,  Y02T10/7241

摘要： When the temperature of an engine and a main battery is low at the time of activating a vehicle system, an ECU starts the engine in advance and outputs a running permission signal after completion of engine startup. At this stage, the ECU suspends a defect diagnosis operation on a subsidiary load and feedback-controls the DC/DC converter by setting the voltage control value to a level lower than the output voltage from the subsidiary battery and at least the lower limit of the operating voltage of the ECU. The ECU feedback-controls the DC/DC converter by setting the voltage control value to a level of at least the output voltage of the subsidiary battery in response to completion of engine start-up. Then, the suspension of the defect diagnosis operation on the subsidiary load is canceled and a running permission signal is output.

摘要翻译： 当在启动车辆系统时发动机和主电池的温度低时，ECU预先启动发动机并在发动机启动完成之后输出行驶允许信号。 在这个阶段，ECU暂停对辅助负载的缺陷诊断操作，并通过将电压控制值设置为低于来自辅助电池的输出电压的电平来反馈控制DC / DC转换器，并且至少下限 ECU的工作电压。 ECU反馈通过将发动机起动结束时的电压控制值设定为至少为辅助电池的输出电压的电平来控制DC / DC转换器。 然后，取消对辅助负载的故障诊断操作的暂停，并输出运行允许信号。

公开(公告)号：US07364798B2

公开(公告)日：2008-04-29

申请号：US11072448

申请日：2005-03-07

申请人： Yoshio Harada ,  Junichi Takeuchi ,  Nobuyuki Nagayama ,  Kouji Mitsuhashi

发明人： Yoshio Harada ,  Junichi Takeuchi ,  Nobuyuki Nagayama ,  Kouji Mitsuhashi

IPC分类号： H01L21/00 ,  B32B3/10

CPC分类号： H01J37/32477 ,  B01J19/02 ,  B01J2219/0218 ,  B01J2219/0236 ,  B01J2219/024 ,  B01J2219/0263 ,  B01J2219/0286 ,  B01J2219/0894 ,  C09D1/00 ,  C23C4/00 ,  C23C4/02 ,  C23C4/11 ,  Y10T428/12458 ,  Y10T428/12479 ,  Y10T428/12549 ,  Y10T428/12618 ,  Y10T428/24999

摘要： It is to propose an internal member for a plasma treating vessel having excellent resistances to chemical corrosion and plasma erosion under an environment containing a halogen gas and an advantageous method of producing the same, which is a member formed by covering a surface of a substrate with a multilayer composite layer consisting of a metal coating formed as an undercoat, Al2O3 film formed on the undercoat as a middle layer and Y2O3 sprayed coating formed on the middle layer as a top coat.

公开(公告)号：US06982499B1

公开(公告)日：2006-01-03

申请号：US09690183

申请日：2000-10-17

申请人： Tadayoshi Kachi ,  Junichi Takeuchi ,  Seiki Sakata

发明人： Tadayoshi Kachi ,  Junichi Takeuchi ,  Seiki Sakata

IPC分类号： H02J7/016

CPC分类号： B60L15/2045 ,  B60L11/1851 ,  B60L2210/10 ,  H02M3/1588 ,  Y02T10/645 ,  Y02T10/7005 ,  Y02T10/7055 ,  Y02T10/7216 ,  Y02T10/7283 ,  Y10T307/516 ,  Y10T307/675

摘要： A power converter that can be used in a vehicle equipped with an electrical motor provides power to both the electrical motor and other, auxiliary loads, such as a headlamp, that require a different voltage. The power converter includes a first DC power supply that generates a first voltage equivalent to the voltage required by the auxiliary loads and a second DC power supply, connected in series with the first DC power supply, that generates a differential voltage, where the sum of the differential voltage and the first voltage is the voltage required to drive the electrical motor. A DC-DC converter is connected to the second power supply and converts the differential voltage to the voltage required to drive the auxiliary loads.

摘要翻译： 可用于配备有电动机的车辆中的电力转换器为需要不同电压的电动机和其它辅助负载（例如前照灯）提供电力。 电力转换器包括：第一直流电源，其产生与辅助负载所需的电压相当的第一电压;以及与第一直流电源串联连接的第二直流电源，其产生差分电压，其中， 差分电压和第一电压是驱动电动机所需的电压。 DC-DC转换器连接到第二电源，并将差分电压转换为驱动辅助负载所需的电压。

公开(公告)号：US06926587B2

公开(公告)日：2005-08-09

申请号：US10803484

申请日：2004-03-18

申请人： Junichi Takeuchi

发明人： Junichi Takeuchi

IPC分类号： B24B37/00 ,  B24B37/04 ,  B24B37/30 ,  B24B57/02 ,  H01L21/304 ,  B24B49/00

CPC分类号： B24B37/04 ,  B24B57/02

摘要： A CMP apparatus is provided for polishing wafers that are substrates to be polished by CMP. The CMP apparatus comprises a stage that is structured to be rotatable and holds a wafer to be polished, a polishing head holding section that holds a polishing head equipped with a polishing pad over the stage, a polishing head storage section that stores replacement polishing heads equipped with polishing pads; and a polishing head replacement mechanism that replaces the polishing head held by the polishing head holding section with the replacement polishing heads stored in the polishing head storage section.

摘要翻译： 提供CMP装置，用于抛光作为通过CMP抛光的基板的晶片。 所述CMP装置包括被构造为能够旋转并保持要抛光的晶片的台，抛光头保持部，其将配备有抛光垫的抛光头保持在所述台上;抛光头存储部，其存储配备有更换的抛光头 带抛光垫; 以及研磨头更换机构，其将由抛光头保持部保持的研磨头替换为存储在抛光头存储部中的替换抛光头。