公开(公告)号：US20210225446A1

公开(公告)日：2021-07-22

申请号：US17205135

申请日：2021-03-18

申请人： Micron Technology, Inc.

发明人： Arup Bhattacharyya

IPC分类号： G11C14/00 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/423

摘要： The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge storage element configured to store a first charge transported from the gate element and through the charge transport element, wherein the first charge storage element includes a nitride material, and a second charge storage element configured to store a second charge transported from the gate element and through the charge transport element, wherein the second charge storage element includes a gallium nitride material.

公开(公告)号：US20200152269A1

公开(公告)日：2020-05-14

申请号：US16744388

申请日：2020-01-16

申请人： Micron Technology, Inc.

发明人： Arup Bhattacharyya

IPC分类号： G11C14/00 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/792

摘要： The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge storage element configured to store a first charge transported from the gate element and through the charge transport element, wherein the first charge storage element includes a nitride material, and a second charge storage element configured to store a second charge transported from the gate element and through the charge transport element, wherein the second charge storage element includes a gallium nitride material.

公开(公告)号：US20200075394A1

公开(公告)日：2020-03-05

申请号：US16675464

申请日：2019-11-06

申请人： Micron Technology, Inc.

发明人： Arup Bhattacharyya

IPC分类号： H01L21/765 ,  H01L21/28 ,  H01L29/40 ,  H01L27/11575 ,  H01L27/11548 ,  H01L21/762 ,  H01L21/763

摘要： The present disclosure includes semiconductor structures and methods of forming semiconductor structures for trench isolation interfaces. An example semiconductor structure includes a semiconductor substrate having a shallow trench isolation (STI) structure with a trench formed therein. A material in the trench forms a charged interface by interaction with the semiconductor substrate of the STI structure. The formed charged interface raises a parasitic threshold of the STI structure.

公开(公告)号：US10541027B2

公开(公告)日：2020-01-21

申请号：US16218125

申请日：2018-12-12

申请人： Micron Technology, Inc.

发明人： Arup Bhattacharyya

IPC分类号： G11C14/00 ,  H01L29/20 ,  H01L29/51 ,  H01L27/11568 ,  H01L27/108 ,  H01L49/02 ,  G11C16/04 ,  H01L29/49

摘要： The present disclosure includes multifunctional memory cells. A number of embodiments include a charge transport element having an oxygen-rich silicon oxynitride material, a volatile charge storage element configured to store a first charge transported through the charge transport element, and a non-volatile charge storage element configured to store a second charge transported through the charge transport element, wherein the non-volatile charge storage element includes a gallium nitride material.

公开(公告)号：US10411026B2

公开(公告)日：2019-09-10

申请号：US15641558

申请日：2017-07-05

申请人： Micron Technology, Inc.

发明人： Arup Bhattacharyya

IPC分类号： H01L27/11568 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/285 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L23/535 ,  H01L29/423 ,  H01L27/11573

摘要： The present disclosure includes methods of forming, and semiconductor structures for, integrated computing structures formed on silicon. An example method includes forming, on a silicon semiconductor material, an integrated computing structure by forming a number of complementary metal-oxide-semiconductor (CMOS) devices including a plurality of materials, forming a non-volatile memory (NVM) device including a plurality of materials, and forming the plurality of materials of the CMOS devices and the plurality of materials of the NVM device from a plurality of same materials shared at a corresponding plurality of positions within the structure. A particular function is provided by each of the plurality of same materials at the corresponding plurality of positions.

公开(公告)号：US20190013234A1

公开(公告)日：2019-01-10

申请号：US15641478

申请日：2017-07-05

申请人： Micron Technology, Inc.

发明人： Arup Bhattacharyya

IPC分类号： H01L21/765 ,  H01L21/763 ,  H01L21/762 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/40

摘要： The present disclosure includes semiconductor structures and methods of forming semiconductor structures for trench isolation interfaces. An example semiconductor structure includes a semiconductor substrate having a shallow trench isolation (STI) structure with a trench formed therein. An material in the trench forms a charged interface by interaction with the semiconductor substrate of the STI structure. The formed charged interface raises a parasitic threshold of the STI structure.

公开(公告)号：US10153039B1

公开(公告)日：2018-12-11

申请号：US15641597

申请日：2017-07-05

申请人： Micron Technology, Inc.

发明人： Arup Bhattacharyya

IPC分类号： G11C11/56 ,  H01L29/51 ,  H01L29/72 ,  H01L29/792 ,  H01L29/49 ,  G11C16/10 ,  G11C16/14 ,  G11C16/04

摘要： The present disclosure includes memory cells programmed via multi-mechanism charge transports. An example apparatus includes a semiconductor material, a tunneling material formed on the semiconductor material, a charge trapping material formed on the tunneling material, a charge blocking material formed on the charge trapping material, and a metal gate formed on the charge blocking material. The charge trapping material comprises gallium nitride (GaN), and the memory cell is programmed to the target state via the multi-mechanism charge transport such that charges are simultaneously transported to the charge trapping material through a plurality of different channels.

公开(公告)号：US20160020322A1

公开(公告)日：2016-01-21

申请号：US14869546

申请日：2015-09-29

申请人： Micron Technology, Inc.

发明人： Arup Bhattacharyya ,  Leonard Forbes ,  Paul A. Farrar

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265

CPC分类号： H01L29/7846 ,  H01L21/26506 ,  H01L21/7621 ,  H01L21/76232 ,  H01L29/0653 ,  H01L29/66568 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

摘要： In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.

摘要翻译： 在各种方法实施例中，限定半导体衬底中的器件区域和与器件区域相邻的隔离区域。 器件区域具有沟道区域，并且隔离区域具有与沟道区域横向相邻的应变诱导区域。 通道区域应变为用于载流子迁移率增强的期望应变，其中至少一种离子型注入能量，从而在隔离区域的应变诱导区域中产生峰值注入。 本文提供了其它方面和实施例。

公开(公告)号：US09231047B2

公开(公告)日：2016-01-05

申请号：US14518723

申请日：2014-10-20

申请人： Micron Technology, Inc.

发明人： Kie Y. Ahn ,  Leonard Forbes ,  Arup Bhattacharyya

IPC分类号： H01L21/02 ,  H01L49/02 ,  C23C16/30 ,  C23C16/40 ,  H01G4/08 ,  H01G4/12 ,  H01G4/33 ,  H01L21/316

CPC分类号： H01L28/60 ,  C23C16/308 ,  C23C16/40 ,  H01G4/085 ,  H01G4/1209 ,  H01G4/33 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02244 ,  H01L21/0228 ,  H01L21/31683 ,  H01L28/40 ,  H01L28/90

摘要： Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

摘要翻译： 示出了通过这些方法形成的形成的电容器和形成的电容器。 将含有镨的单层沉积在基底上，随后进行处理以形成氧化镨电介质。 将含有钛或其他金属的单层沉积在基底上，随后加工形成金属电极。 所得的电容器结构包括诸如改进的尺寸控制的特性。 一个改进的尺寸控制包括厚度。 一些所得的电容器结构还包括诸如无定形或纳米晶体微结构的性质。 使用这些方法形成的电容器的选定部件具有比衬底形貌更好的阶梯覆盖和更强的膜机械性能。

公开(公告)号：US11264472B2

公开(公告)日：2022-03-01

申请号：US16937243

申请日：2020-07-23

申请人： Micron Technology, Inc.

发明人： Arup Bhattacharyya

IPC分类号： H01L29/423 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L27/11582

摘要： In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.