公开(公告)号：US07307312B2

公开(公告)日：2007-12-11

申请号：US10817904

申请日：2004-04-06

申请人： Mikimasa Suzuki ,  Yoshiyuki Hattori ,  Kyoko Nakashima

发明人： Mikimasa Suzuki ,  Yoshiyuki Hattori ,  Kyoko Nakashima

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L29/7811 ,  H01L21/78 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device manufacturing method comprises forming a pn column so that the pn column is designed to have a strip form in the section of the substrate and have a repetitive pattern of a p-conduction type and an n-conduction type on the substrate surface over an area where plural semiconductor devices having the same structure are formed in a semiconductor substrate, forming residual constituent elements of the plural semiconductor devices having the same structure in areas where the repetitive patterns are located while the pn column serves as a part of the constituent element of each semiconductor device, and dicing the individual semiconductor devices into chips from the area where the plural semiconductor devices having the same structure are formed.

摘要翻译： 半导体器件制造方法包括形成pn列，使得pn列被设计为在衬底的部分中具有条形，并且在衬底表面上具有p导电型和n导电型的重复图案， 在半导体衬底中形成具有相同结构的多个半导体器件的区域，在pn列用作构成元件的一部分的同时，在重复图案所在的区域中形成具有相同结构的多个半导体器件的残留构成元件 并且从形成有相同结构的多个半导体器件的区域将各个半导体器件切割成芯片。

公开(公告)号：US20050077572A1

公开(公告)日：2005-04-14

申请号：US10960286

申请日：2004-10-08

申请人： Shoichi Yamauchi ,  Mikimasa Suzuki ,  Yoshiyuki Hattori ,  Kyoko Nakashima

发明人： Shoichi Yamauchi ,  Mikimasa Suzuki ,  Yoshiyuki Hattori ,  Kyoko Nakashima

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L29/49

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7813

摘要： A device includes a center portion, and a periphery portion disposed around the center portion. The periphery portion includes a first semiconductor layer, an intermediate layer, a second semiconductor layer, an insulation layer and an electrode. The intermediate layer includes a periodic construction having a first region and a second region. The center portion includes a contact region. The electrode extends to the periphery portion to have an extension length of the electrode between the contact region and a periphery of the electrode. The extension length of the electrode is equal to or longer than one-eighth of a distance between the contact region and an outer periphery of the periodic construction.

摘要翻译： 装置包括中心部分和围绕中心部分设置的周边部分。 周边部分包括第一半导体层，中间层，第二半导体层，绝缘层和电极。 中间层包括具有第一区域和第二区域的周期性结构。 中心部分包​​括接触区域。 电极延伸到周边部分，以使得电极在接触区域和电极周边之间具有延伸长度。 电极的延伸长度等于或长于接触区域和周期性构造的外周之间的距离的八分之一。

公开(公告)号：US20050133859A1

公开(公告)日：2005-06-23

申请号：US11012116

申请日：2004-12-16

申请人： Makoto Kuwahara ,  Yoshiyuki Hattori ,  Shoichi Yamauchi ,  Mikimasa Suzuki

发明人： Makoto Kuwahara ,  Yoshiyuki Hattori ,  Shoichi Yamauchi ,  Mikimasa Suzuki

IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L29/06 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7813 ,  G06F17/5068 ,  H01L29/0634

摘要： A semiconductor device is fabricated to include a withstand-voltage assurance layer designed into a multi-dimensional super junction structure and a group of trench gate electrodes, each of which penetrating a body layer in contact with the multi-dimensional super junction structure to reach the multi-dimensional super junction structure, so that dispersions of an on-resistance of the semiconductor device can be reduced. When a position at which the group of trench gate electrodes is created is shifted in one direction, the size of an overlap area common to the group of trench gate electrodes and an n-type column changes. However, the group of trench gate electrodes is oriented in such a way that the changes in overlap-area size are minimized.

摘要翻译： 半导体器件被制造成包括设计成多维超结结构的耐压保证层和一组沟槽栅极电极，每个沟槽栅电极穿透与多维超结结构接触的体层以达到 多维超结结构，能够降低半导体装置的导通电阻的分散。 当形成沟槽栅电极组的位置在一个方向上移动时，沟槽栅电极组和n型列共同的重叠区域的尺寸改变。 然而，沟槽栅电极组被定向成使得重叠区域尺寸的变化最小化。

公开(公告)号：US07364971B2

公开(公告)日：2008-04-29

申请号：US11356984

申请日：2006-02-21

申请人： Hitoshi Yamaguchi ,  Mikimasa Suzuki ,  Yoshiyuki Hattori

发明人： Hitoshi Yamaguchi ,  Mikimasa Suzuki ,  Yoshiyuki Hattori

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/1095

摘要： A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.

摘要翻译： 半导体器件包括主体区域，具有第一部分和第二部分的漂移区域以及沟槽栅电极。 身体区域设置在漂移区域上。 第一和第二部分沿延伸方向延伸，使得第二部分与第一部分相邻。 沟槽栅电极穿透体区并到达漂移区，使得沟槽栅电极通过绝缘层面向体区和漂移区。 沟槽栅电极沿与第一和第二部分的延伸方向交叉的方向延伸。 第一部分包括沟槽栅电极附近的部分，其杂质浓度等于或低于体区的杂质浓度。

公开(公告)号：US20050006717A1

公开(公告)日：2005-01-13

申请号：US10872789

申请日：2004-06-22

申请人： Hitoshi Yamaguchi ,  Mikimasa Suzuki ,  Yoshiyuki Hattori

发明人： Hitoshi Yamaguchi ,  Mikimasa Suzuki ,  Yoshiyuki Hattori

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8242

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/1095

摘要： A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.

摘要翻译： 半导体器件包括主体区域，具有第一部分和第二部分的漂移区域以及沟槽栅电极。 身体区域设置在漂移区域上。 第一和第二部分沿延伸方向延伸，使得第二部分与第一部分相邻。 沟槽栅电极穿透体区并到达漂移区，使得沟槽栅电极通过绝缘层面向体区和漂移区。 沟槽栅电极沿与第一和第二部分的延伸方向交叉的方向延伸。 第一部分包括沟槽栅电极附近的部分，其杂质浓度等于或低于体区的杂质浓度。

公开(公告)号：US07345339B2

公开(公告)日：2008-03-18

申请号：US10872789

申请日：2004-06-22

申请人： Hitoshi Yamaguchi ,  Mikimasa Suzuki ,  Yoshiyuki Hattori

发明人： Hitoshi Yamaguchi ,  Mikimasa Suzuki ,  Yoshiyuki Hattori

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/1095

摘要： A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.

摘要翻译： 半导体器件包括主体区域，具有第一部分和第二部分的漂移区域以及沟槽栅电极。 身体区域设置在漂移区域上。 第一和第二部分沿延伸方向延伸，使得第二部分与第一部分相邻。 沟槽栅电极穿透体区并到达漂移区，使得沟槽栅电极通过绝缘层面向体区和漂移区。 沟槽栅电极沿与第一和第二部分的延伸方向交叉的方向延伸。 第一部分包括沟槽栅电极附近的部分，其杂质浓度等于或低于体区的杂质浓度。

公开(公告)号：US07342265B2

公开(公告)日：2008-03-11

申请号：US11012116

申请日：2004-12-16

申请人： Makoto Kuwahara ,  Yoshiyuki Hattori ,  Shoichi Yamauchi ,  Mikimasa Suzuki

发明人： Makoto Kuwahara ,  Yoshiyuki Hattori ,  Shoichi Yamauchi ,  Mikimasa Suzuki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  G06F17/5068 ,  H01L29/0634

摘要： A semiconductor device is fabricated to include a withstand-voltage assurance layer designed into a multi-dimensional super junction structure and a group of trench gate electrodes, each of which penetrating a body layer in contact with the multi-dimensional super junction structure to reach the multi-dimensional super junction structure, so that dispersions of an on-resistance of the semiconductor device can be reduced. When a position at which the group of trench gate electrodes is created is shifted in one direction, the size of an overlap area common to the group of trench gate electrodes and an n-type column changes. However, the group of trench gate electrodes is oriented in such a way that the changes in overlap-area size are minimized.

摘要翻译： 半导体器件被制造成包括设计成多维超结结构的耐压保证层和一组沟槽栅极电极，每个沟槽栅电极穿透与多维超结结构接触的体层以达到 多维超结结构，能够降低半导体装置的导通电阻的分散。 当形成沟槽栅电极组的位置在一个方向上移动时，沟槽栅电极组和n型列共同的重叠区域的尺寸改变。 然而，沟槽栅电极组被定向成使得重叠区域尺寸的变化最小化。

公开(公告)号：US06864532B2

公开(公告)日：2005-03-08

申请号：US10175294

申请日：2002-06-20

申请人： Takaaki Aoki ,  Akira Kuroyanagi ,  Mikimasa Suzuki ,  Takafumi Arakawa ,  Yukio Tsuzuki

发明人： Takaaki Aoki ,  Akira Kuroyanagi ,  Mikimasa Suzuki ,  Takafumi Arakawa ,  Yukio Tsuzuki

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/739 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L29/7813 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/7397

摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.

摘要翻译： 沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。 栅极绝缘膜包括位于沟槽的壁上的第一部分和位于沟槽的上部和底部的第二部分。 第一部分包括第一氧化膜，氮化物膜和第二氧化物膜。 第二部分仅包括氧化膜并且比第一部分厚。 因此，可以减小沟槽的上下角部的电场集中以提高耐压。 此外，沟槽的端部可以具有比第一部分更厚的绝缘层。

公开(公告)号：US07148125B2

公开(公告)日：2006-12-12

申请号：US10310021

申请日：2002-12-05

申请人： Mikimasa Suzuki ,  Chikage Noritake

发明人： Mikimasa Suzuki ,  Chikage Noritake

IPC分类号： H01L21/46 ,  H01L21/302

CPC分类号： H01L29/7813 ,  H01L21/02035 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/66348

摘要： A semiconductor device, which has a relatively low ON resistance, is manufactured using the following steps. First, a semiconductor wafer that includes a semiconductor layer and a semiconductor element layer, which is located on the semiconductor layer, is formed. Then, the wafer is ground evenly to a predetermined thickness from the side where the semiconductor layer is located. Next, the wafer is etched to a predetermined thickness from the side where the semiconductor layer is located while the periphery of the wafer is masked against the etchant to form a rim at the periphery. The wafer is reinforced by the rim at the periphery, so even if the wafer is relatively large, the wafer is prevented from breaking or warping at the later steps after the wafer is thinned by etching.

公开(公告)号：US06972459B2

公开(公告)日：2005-12-06

申请号：US10164313

申请日：2002-06-07

申请人： Shoji Miura ,  Mikimasa Suzuki ,  Akira Kuroyanagi ,  Yoshitaka Nakano

发明人： Shoji Miura ,  Mikimasa Suzuki ,  Akira Kuroyanagi ,  Yoshitaka Nakano

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/32 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/32 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A drift layer is formed on a substrate. A base region is formed on the drift layer. A plurality of source regions are formed in a surficial layer of the base region. A plurality of gate electrodes face to the base region and the source region via a gate insulating film. A source electrode is brought into contact with the base region and the source region. A nitrogen cluster containing layer is embedded in the drift layer so as to extend laterally under the base region so that at least part of the drift region is left under the nitrogen cluster containing layer.

摘要翻译： 在基板上形成漂移层。 在漂移层上形成基极区域。 多个源极区域形成在基极区域的表面层中。 多个栅电极经由栅极绝缘膜与基极区域和源极区域面对。 源电极与基极区域和源极区域接触。 含氮簇层包含在漂移层中，以在基底区域横向延伸，使得漂移区的至少一部分留在含氮簇层的下方。