公开(公告)号：US08288800B2

公开(公告)日：2012-10-16

申请号：US12651487

申请日：2010-01-04

申请人： Ming Zhu ,  Chun Shan Yin ,  Elgin Quek ,  Shyue Seng Tan

发明人： Ming Zhu ,  Chun Shan Yin ,  Elgin Quek ,  Shyue Seng Tan

IPC分类号： H01L29/66

CPC分类号： H01L29/7885 ,  H01L21/28273 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785

摘要： A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are formed. The first current path serves a first purpose and the second current path serves a second purpose. The gate controls selection of the current paths.

摘要翻译： 公开了一种形成装置的方法。 该方法包括提供具有活性区域的基底。 在基板上形成栅极。 形成通过栅极的第一和第二电流路径。 第一电流通路用于第一目的，第二电流通路用于第二目的。 门控制当前路径的选择。

公开(公告)号：US08368127B2

公开(公告)日：2013-02-05

申请号：US12587511

申请日：2009-10-08

申请人： Ming Zhu ,  Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

发明人： Ming Zhu ,  Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

IPC分类号： H01L29/76

CPC分类号： H01L21/26586 ,  B82Y10/00 ,  H01L29/0895 ,  H01L29/7391 ,  H01L29/7606 ,  H01L29/7613

摘要： A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id).

摘要翻译： 制造TFET器件的方法（和半导体器件）提供了一个源极区，其源极区至少有一部分位于栅极电介质的下面。 在一个实施例中，TFET在硅衬底中包括N +漏极区域和P +源极区域，其中N +漏极区域是硅并且P +源极区域是硅锗（SiGe）。 源区包括第一类型的第一区域（例如，P + SiGe）和第二类型（未掺杂的SiGe）的第二区域，其中源极区域的至少一部分位于栅极电介质的下方。 该结构降低了隧道势垒宽度并增加了驱动电流（Id）。

公开(公告)号：US20110084319A1

公开(公告)日：2011-04-14

申请号：US12587511

申请日：2009-10-08

申请人： Ming Zhu ,  Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

发明人： Ming Zhu ,  Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26586 ,  B82Y10/00 ,  H01L29/0895 ,  H01L29/7391 ,  H01L29/7606 ,  H01L29/7613

摘要： A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id).

摘要翻译： 制造TFET器件的方法（和半导体器件）提供了一个源极区，其源极区至少有一部分位于栅极电介质的下面。 在一个实施例中，TFET在硅衬底中包括N +漏极区域和P +源极区域，其中N +漏极区域是硅并且P +源极区域是硅锗（SiGe）。 源区包括第一类型的第一区域（例如，P + SiGe）和第二类型（未掺杂的SiGe）的第二区域，其中源极区域的至少一部分位于栅极电介质的下方。 该结构降低了隧道势垒宽度并增加了驱动电流（Id）。

公开(公告)号：US09159565B2

公开(公告)日：2015-10-13

申请号：US12544747

申请日：2009-08-20

申请人： Shyue Seng Tan ,  Lee Wee Teo ,  Ming Zhu

发明人： Shyue Seng Tan ,  Lee Wee Teo ,  Ming Zhu

IPC分类号： H01L29/76 ,  H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26586 ,  H01L29/34 ,  H01L29/66356 ,  H01L29/7391

摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate; implanting a well region, having a first conductivity, on the semiconductor substrate; patterning a gate oxide layer on the well region; implanting a source, having a second conductivity, at an angle for implanting under the gate oxide layer; selectively implanting a dopant pocket, having a third conductivity that is opposite the second conductivity, at the angle for forming the dopant pocket under the gate oxide layer; and implanting a drain, having the third conductivity, for forming a transistor channel asymmetrically positioned under the gate oxide layer.

摘要翻译： 一种集成电路系统的制造方法，包括：提供半导体衬底; 在所述半导体衬底上注入具有第一导电性的阱区; 在阱区上形成栅极氧化物层; 以一角度植入具有第二导电性的源，用于注入在栅极氧化物层下方; 选择性地注入具有与第二导电性相反的第三导电性的掺杂剂凹坑，以形成栅极氧化物层下面的掺杂剂口袋的角度; 以及注入具有第三导电性的漏极，以形成不对称地位于栅极氧化物层下方的晶体管沟道。

公开(公告)号：US20110042757A1

公开(公告)日：2011-02-24

申请号：US12544747

申请日：2009-08-20

申请人： Shyue Seng Tan ,  Lee Wee Teo ,  Ming Zhu

发明人： Shyue Seng Tan ,  Lee Wee Teo ,  Ming Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/34 ,  H01L29/66356 ,  H01L29/7391

摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate; implanting a well region, having a first conductivity, on the semiconductor substrate; patterning a gate oxide layer on the well region; implanting a source, having a second conductivity, at an angle for implanting under the gate oxide layer; selectively implanting a dopant pocket, having a third conductivity that is opposite the second conductivity, at the angle for forming the dopant pocket under the gate oxide layer; and implanting a drain, having the third conductivity, for forming a transistor channel asymmetrically positioned under the gate oxide layer.

摘要翻译： 一种集成电路系统的制造方法，包括：提供半导体衬底; 在所述半导体衬底上注入具有第一导电性的阱区; 在阱区上形成栅极氧化物层; 以一角度植入具有第二导电性的源，用于注入在栅极氧化物层下方; 选择性地注入具有与第二导电性相反的第三导电性的掺杂剂凹坑，以形成栅极氧化物层下面的掺杂剂口袋的角度; 以及注入具有第三导电性的漏极，以形成不对称地位于栅极氧化物层下方的晶体管沟道。

公开(公告)号：US09196611B2

公开(公告)日：2015-11-24

申请号：US14250519

申请日：2014-04-11

申请人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

发明人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

IPC分类号： H01L31/119 ,  H01L27/06 ,  H01L23/522 ,  H01L27/02 ,  H01L27/08

CPC分类号： H01L27/0617 ,  H01L23/5227 ,  H01L27/0207 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

摘要翻译： 本公开为半导体器件中的电感器提供了减少的衬底耦合。 制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。 该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。 该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光刻胶（PR）层。 然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以 形成在不包括金属栅极的第二区域上。

公开(公告)号：US20140054711A1

公开(公告)日：2014-02-27

申请号：US13594289

申请日：2012-08-24

申请人： Harry Hak-Lay Chuang ,  Ming Zhu

发明人： Harry Hak-Lay Chuang ,  Ming Zhu

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7391 ,  H01L21/823418 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/7889

摘要： A semiconductor device cell is disclosed. The semiconductor device cell includes a transistor gate having a gating surface and a contacting surface and a source region contacted by a source contact. The semiconductor device cell further includes a drain region contacted by a drain contact, wherein the drain contact is not situated opposite the source contact with respect to the gating surface of the transistor gate. Additional semiconductor device cells in which the gate contact is closer to the source contact than to the drain contact are disclosed.

摘要翻译： 公开了一种半导体器件单元。 半导体器件单元包括晶体管栅极，其具有门控表面和接触表面以及与源极接触的源极区域。 半导体器件单元还包括与漏极接触接触的漏极区，其中漏极接触件不相对于晶体管栅极的选通表面与源极接触相对。 公开了其中栅极接触比漏极接触更靠近源极接触的其它半导体器件单元。

公开(公告)号：US20140042524A1

公开(公告)日：2014-02-13

申请号：US13568997

申请日：2012-08-07

申请人： Hak-Lay Chuang ,  Ming Zhu ,  Yi-Ren Chen

发明人： Hak-Lay Chuang ,  Ming Zhu ,  Yi-Ren Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/28114 ,  H01L21/76885 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/42376

摘要： A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum structure. The conical frustum structure includes a drain formed at a bottom portion of the conical frustum, a source formed at a top portion of the vertical conical frustum, and a channel formed at a middle portion of the conical frustum connecting the source and the drain. The GAA structure overlaps with the source at one side of the GAA structure, crosses over the channel, and overlaps with the drain at another side of the GAA structure.

摘要翻译： 一种器件包括晶片衬底，形成在晶片衬底中的锥形截头锥体结构，以及围绕锥形截头锥体结构的中间部分的栅极全能（GAA）结构。 锥形截头锥体结构包括形成在锥形截头锥体的底部处的排水口，形成在垂直锥形截头锥体的顶部处的源和形成在连接源极和漏极的锥形截头锥体的中间部分处的通道。 GAA结构与GAA结构一侧的源重叠，与沟道交叉，并与GAA结构另一侧的漏极重叠。

公开(公告)号：US20130264652A1

公开(公告)日：2013-10-10

申请号：US13440848

申请日：2012-04-05

申请人： Ming Zhu ,  Jyun-Ming Lin ,  Wei Cheng Wu ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Ming Zhu ,  Jyun-Ming Lin ,  Wei Cheng Wu ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L27/092

CPC分类号： H01L29/4941 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

公开(公告)号：US20130260547A1

公开(公告)日：2013-10-03

申请号：US13434344

申请日：2012-03-29

申请人： Sheng-Chen Chung ,  Ming Zhu ,  Jyun-Ming Lin ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Sheng-Chen Chung ,  Ming Zhu ,  Jyun-Ming Lin ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

摘要： A method of semiconductor device fabrication including providing a substrate having a gate dielectric layer such as a high-k dielectric disposed thereon. A tri-layer element is formed on the gate dielectric layer. The tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layer. One of an nFET and a pFET gate structure are formed using the tri-layer element, for example, the second capping layer and the metal gate layer may form a work function layer for one of an nFET and a pFET device. The first capping layer may be a sacrificial layer used to pattern the metal gate layer.

摘要翻译： 一种半导体器件制造方法，包括提供具有栅极电介质层的衬底，例如设置在其上的高k电介质。 在栅介质层上形成三层元件。 三层元件包括第一覆盖层，第二覆盖层和插入第一和第二覆盖层的金属栅极层。 使用三层元件形成nFET和pFET栅极结构之一，例如，第二覆盖层和金属栅极层可以形成nFET和pFET器件中的一个的功函数层。 第一覆盖层可以是用于图案化金属栅极层的牺牲层。