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46 条记录 (耗时 0.017 秒)

    Trim process for critical dimension control for integrated circuits
    1.
    发明申请
    Trim process for critical dimension control for integrated circuits 失效
    用于集成电路的关键尺寸控制的修整过程

    公开(公告)号：US20070212889A1

    公开(公告)日：2007-09-13

    申请号：US11372825

    申请日：2006-03-09

    申请人： Mirzafer Abatchev ,  Krupakar Subramanian ,  Baosuo Zhou

    发明人： Mirzafer Abatchev ,  Krupakar Subramanian ,  Baosuo Zhou

    IPC分类号： H01L21/467

    CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139

    摘要： Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.

    摘要翻译： 公开了采用用于集成电路的关键尺寸控制的修整工艺的衬底的蚀刻方法。 在一个实施例中，蚀刻方法包括在目标层上提供第一硬掩模层; 在第一硬掩模层上提供第二硬掩模层; 在所述第二硬掩模层上提供光致抗蚀剂层; 在光致抗蚀剂层中形成图案; 将图案转移到第二硬掩模层中; 以及在所述第二硬掩模层的顶部上用所述光致抗蚀剂层修剪所述第二硬掩模层。 第二硬掩模层的顶表面由光致抗蚀剂保护，并且衬底在修整蚀刻期间被上覆的第一硬掩模层保护，因此可以是侵蚀性的。

    Method of depositing a layer comprising silicon, carbon, and flourine onto a semiconductor substrate
    4.
    发明申请
    Method of depositing a layer comprising silicon, carbon, and flourine onto a semiconductor substrate 失效
    将包含硅，碳和矾土的层沉积到半导体衬底上的方法

    公开(公告)号：US20070066068A1

    公开(公告)日：2007-03-22

    申请号：US11601362

    申请日：2006-11-16

    申请人： Mirzafer Abatchev ,  Krupakar Subramanian

    发明人： Mirzafer Abatchev ,  Krupakar Subramanian

    IPC分类号： C03C25/68 ,  B01F17/00 ,  H01L21/311 ,  H01L21/302

    CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/3148

    摘要： The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing sidewalls, and a base. A layer comprising SixCyFz is deposited over the feature, where “x” is from 0 to 0.2, “y” is from 0.3 to 0.9, and “z” is from 0.1 to 0.6. The SixCyFz—comprising layer and upper portions of the feature opposing sidewalls are etched effective to laterally recess such upper portions proximate the feature top relative to lower portions of the feature opposing sidewalls proximate the feature base. After such etching of the SixCyFz—comprising layer and such etching of upper portions of the feature sidewalls, the substrate is etched using the masking feature as a mask.

    摘要翻译： 本发明包括蚀刻衬底的方法，在衬底上形成特征的方法，以及将包含硅，碳和氟的层沉积到半导体衬底上的方法。 在一个实施方案中，蚀刻方法包括形成从基板突出的掩模特征。 该特征具有顶部，相对的侧壁和基部。 在特征上沉积包含Si x Si x F z的层，其中“x”为0至0.2，“y”为 0.3〜0.9，“z”为0.1〜0.6。 有意义的是，具有相同特征的Si层和顶部相对侧壁的上部被有效地横向凹入靠近 特征是相对于靠近特征基部的相对侧壁的特征的下部。 在这种蚀刻Si x SiCl 3 Z z-x元素层并蚀刻特征侧壁的上部之后，蚀刻基板 使用屏蔽功能作为掩码。

    Nanoimprint lithography template techniques for use during the fabrication of a semiconductor device and systems including same
    5.
    发明申请
    Nanoimprint lithography template techniques for use during the fabrication of a semiconductor device and systems including same 失效
    在制造半导体器件期间使用的纳米压印光刻模板技术及包括其的系统

    公开(公告)号：US20070049028A1

    公开(公告)日：2007-03-01

    申请号：US11214684

    申请日：2005-08-30

    申请人： Krupakar Subramanian ,  Mirzafer Abatchev

    发明人： Krupakar Subramanian ,  Mirzafer Abatchev

    IPC分类号： B44C1/22 ,  B05C1/00 ,  H01L21/302

    CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  Y10S977/887 ,  Y10S977/888

    摘要： A method for forming a template useful for nanoimprint lithography comprises forming at least one pillar which provides a topographic feature extending from a template base. At least one conformal pattern layer and one conformal spacing layer, and generally a plurality of alternating pattern layers and spacing layers, are formed over the template base and pillar. A planarized filler layer is formed over the pattern and spacing layers, then the filler, the spacing layer and the pattern layer are partially removed, for example using mechanical polishing, to expose the pillar. One or more etches are performed to remove at least a portion of the pillar, the filler, and the spacing layer to result in the pattern layer protruding from the spacing layer and providing the template pattern.

    摘要翻译： 用于形成用于纳米压印光刻的模板的方法包括形成提供从模板基底延伸的地形特征的至少一个柱。 在模板基底和柱上方形成至少一个共形图案层和一个共形间隔层，以及通常多个交替图案层和间隔层。 在图案和间隔层之上形成平坦化的填充层，然后例如使用机械抛光部分去除填料，间隔层和图案层以暴露柱。 执行一个或多个蚀刻以去除柱，填料和间隔层的至少一部分，以导致图案层从间隔层突出并提供模板图案。

    METHOD OF ETCHING A SUBSTRATE AND METHOD OF FORMING A FEATURE ON A SUBSTRATE
    7.
    发明申请
    METHOD OF ETCHING A SUBSTRATE AND METHOD OF FORMING A FEATURE ON A SUBSTRATE 有权
    蚀刻基板的方法和在基板上形成特征的方法

    公开(公告)号：US20070042605A1

    公开(公告)日：2007-02-22

    申请号：US11206414

    申请日：2005-08-18

    申请人： Mirzafer Abatchev ,  Krupakar Subramanian

    发明人： Mirzafer Abatchev ,  Krupakar Subramanian

    IPC分类号： C03C25/68 ,  C03C15/00 ,  H01L21/311 ,  H01L21/302

    CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/3148

    摘要： The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing sidewalls, and a base. A layer comprising SixCyFz is deposited over the feature, where “x” is from 0 to 0.2, “y” is from 0.3 to 0.9, and “z” is from 0.1 to 0.6. The SixCyFz-comprising layer and upper portions of the feature opposing sidewalls are etched effective to laterally recess such upper portions proximate the feature top relative to lower portions of the feature opposing sidewalls proximate the feature base. After such etching of the SixCyFz-comprising layer and such etching of upper portions of the feature sidewalls, the substrate is etched using the masking feature as a mask.

    摘要翻译： 本发明包括蚀刻衬底的方法，在衬底上形成特征的方法，以及将包含硅，碳和氟的层沉积到半导体衬底上的方法。 在一个实施方案中，蚀刻方法包括形成从基板突出的掩模特征。 该特征具有顶部，相对的侧壁和基部。 在特征上沉积包含Si x Si x F z的层，其中“x”为0至0.2，“y”为 0.3〜0.9，“z”为0.1〜0.6。 有意义的是，具有相同特征的Si层和顶部相对侧壁的上部被有效地横向凹入靠近 特征是相对于靠近特征基部的相对侧壁的特征的下部。 在这种蚀刻Si x SiCl 3 Z z-x元素层并蚀刻特征侧壁的上部之后，蚀刻基板 使用屏蔽功能作为掩码。