公开(公告)号：US20070212889A1

公开(公告)日：2007-09-13

申请号：US11372825

申请日：2006-03-09

申请人： Mirzafer Abatchev ,  Krupakar Subramanian ,  Baosuo Zhou

发明人： Mirzafer Abatchev ,  Krupakar Subramanian ,  Baosuo Zhou

IPC分类号： H01L21/467

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139

摘要： Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.

摘要翻译： 公开了采用用于集成电路的关键尺寸控制的修整工艺的衬底的蚀刻方法。 在一个实施例中，蚀刻方法包括在目标层上提供第一硬掩模层; 在第一硬掩模层上提供第二硬掩模层; 在所述第二硬掩模层上提供光致抗蚀剂层; 在光致抗蚀剂层中形成图案; 将图案转移到第二硬掩模层中; 以及在所述第二硬掩模层的顶部上用所述光致抗蚀剂层修剪所述第二硬掩模层。 第二硬掩模层的顶表面由光致抗蚀剂保护，并且衬底在修整蚀刻期间被上覆的第一硬掩模层保护，因此可以是侵蚀性的。

公开(公告)号：US20070049032A1

公开(公告)日：2007-03-01

申请号：US11219604

申请日：2005-09-01

申请人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar Subramanian

发明人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar Subramanian

IPC分类号： H01L21/302

CPC分类号： H01L21/31051 ,  H01L21/0337 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49176 ,  Y10T29/4922 ,  Y10T29/49224

摘要： Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

摘要翻译： 可以使用各种图案转移和蚀刻步骤来产生特征。 传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。 公开了使用填充层和保护层的平面化技术。 具有不同高度的集成电路的部分可以被蚀刻到公共平面。

公开(公告)号：US20070123050A1

公开(公告)日：2007-05-31

申请号：US11272980

申请日：2005-11-14

申请人： Baosuo Zhou ,  Mirzafer Abatchev ,  Krupakar Subramanian

发明人： Baosuo Zhou ,  Mirzafer Abatchev ,  Krupakar Subramanian

IPC分类号： C23F1/00 ,  H01L29/04 ,  H01L21/461 ,  B44C1/22 ,  H01L31/036

CPC分类号： H01L21/31144 ,  H01L21/02126 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/3146 ,  H01L27/10852 ,  H01L28/84

摘要： A carbon or carbon-containing underlayer, which is used as a mask, is patterned using a process comprising, in one specific embodiment, boron trichloride and oxygen under specified processing conditions to etch the underlayer. The underlayer is then used as a mask to etch a layer below the underlayer, such as a semiconductor wafer or a layer formed as part of a semiconductor wafer substrate assembly. Various processing conditions are described, as is the formation of various features using embodiments of the inventive process.

摘要翻译： 用作掩模的含碳或碳的底层使用包括在一个具体实施方案中的三氯化硼和氧气在特定加工条件下蚀刻底层的方法进行图案化。 然后将底层用作掩模以蚀刻底层以下的层，例如半导体晶片或形成为半导体晶片衬底组件的一部分的层。 描述了各种处理条件，使用本发明方法的实施例形成各种特征。

公开(公告)号：US20110294294A1

公开(公告)日：2011-12-01

申请号：US13207627

申请日：2011-08-11

申请人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar M. Subramanian

发明人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar M. Subramanian

IPC分类号： H01L21/311 ,  H01L21/306

CPC分类号： H01L21/31051 ,  H01L21/0337 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49176 ,  Y10T29/4922 ,  Y10T29/49224

摘要： Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

摘要翻译： 可以使用各种图案转移和蚀刻步骤来产生特征。 传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。 公开了使用填充层和保护层的平面化技术。 具有不同高度的集成电路的部分可以被蚀刻到公共平面。

公开(公告)号：US20080261349A1

公开(公告)日：2008-10-23

申请号：US12123021

申请日：2008-05-19

申请人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar M. Subramanian

发明人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar M. Subramanian

IPC分类号： H05K3/00 ,  H01L21/00

CPC分类号： H01L21/31051 ,  H01L21/0337 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49176 ,  Y10T29/4922 ,  Y10T29/49224

摘要： Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

摘要翻译： 可以使用各种图案转移和蚀刻步骤来产生特征。 传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。 公开了使用填充层和保护层的平面化技术。 具有不同高度的集成电路的部分可以被蚀刻到公共平面。

公开(公告)号：US08479384B2

公开(公告)日：2013-07-09

申请号：US13207627

申请日：2011-08-11

申请人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar M. Subramanian

发明人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar M. Subramanian

IPC分类号： H05K3/20

CPC分类号： H01L21/31051 ,  H01L21/0337 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49176 ,  Y10T29/4922 ,  Y10T29/49224

摘要： Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

公开(公告)号：US08011090B2

公开(公告)日：2011-09-06

申请号：US12123021

申请日：2008-05-19

申请人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar M. Subramanian

发明人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar M. Subramanian

IPC分类号： H05K3/02 ,  H05K3/10

CPC分类号： H01L21/31051 ,  H01L21/0337 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49176 ,  Y10T29/4922 ,  Y10T29/49224

摘要： Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

摘要翻译： 可以使用各种图案转移和蚀刻步骤来产生特征。 传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。 公开了使用填充层和保护层的平面化技术。 具有不同高度的集成电路的部分可以被蚀刻到公共平面。

公开(公告)号：US07393789B2

公开(公告)日：2008-07-01

申请号：US11219604

申请日：2005-09-01

申请人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar M. Subramanian

发明人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar M. Subramanian

IPC分类号： H01L21/311 ,  H01L21/762

CPC分类号： H01L21/31051 ,  H01L21/0337 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49176 ,  Y10T29/4922 ,  Y10T29/49224

摘要： Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

摘要翻译： 可以使用各种图案转移和蚀刻步骤来产生特征。 传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。 公开了使用填充层和保护层的平面化技术。 具有不同高度的集成电路的部分可以被蚀刻到公共平面。

公开(公告)号：US08852851B2

公开(公告)日：2014-10-07

申请号：US11484271

申请日：2006-07-10

申请人： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph N. Greeley ,  Brian J. Coppa

发明人： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph N. Greeley ,  Brian J. Coppa

IPC分类号： H01L21/033 ,  H01L21/308

CPC分类号： H01L21/30625 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

摘要翻译： 图案化层的方法使用一系列自对准间隔物增加在初始图案化层上形成的特征的密度。 提供待蚀刻的层，然后在待蚀刻的层上形成例如使用光学光刻形成的初始牺牲图案形成层。 根据实施例，图案化层可以被修整，然后形成并蚀刻一系列间隔层。 间隔层的数量及其目标尺寸取决于所需的特征密度增加。 还描述了一种过程中半导体器件和电子系统。

公开(公告)号：US08492278B2

公开(公告)日：2013-07-23

申请号：US12749923

申请日：2010-03-30

申请人： Farrell Good ,  Baosuo Zhou ,  Xiaolong Fang ,  Fatma Arzum Simsek-Ege

发明人： Farrell Good ,  Baosuo Zhou ,  Xiaolong Fang ,  Fatma Arzum Simsek-Ege

IPC分类号： H01L21/311

CPC分类号： H01L21/768 ,  H01L21/0332 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/302 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11568

摘要： A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.