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    Semiconductor memory device, circuit board mounted with semiconductor memory device, and method for testing interconnection between a semiconductor memory device with a circuit board
    1.
    发明授权
    Semiconductor memory device, circuit board mounted with semiconductor memory device, and method for testing interconnection between a semiconductor memory device with a circuit board 有权
    半导体存储器件，安装有半导体存储器件的电路板以及用于测试半导体存储器件与电路板之间的互连的方法

    公开(公告)号：US06208571B1

    公开(公告)日：2001-03-27

    申请号：US09500467

    申请日：2000-02-09

    申请人： Mitsutaka Ikeda ,  Tsutomu Taniguchi ,  Yoshikazu Homma

    发明人： Mitsutaka Ikeda ,  Tsutomu Taniguchi ,  Yoshikazu Homma

    IPC分类号： G11C700

    CPC分类号： G01R31/31717 ,  G01R31/2853 ,  G01R31/31701 ,  G01R31/31905

    摘要： A semiconductor memory device comprises a detecting unit and a testing unit. The detecting unit detects a plurality of times a state of a predetermined terminal when the power is switched on, and activates the testing unit when all results of the detections show expected values. The device shifts to a connection testing mode by activation of the testing unit, and performs predetermined testing. Therefore, the testing can be performed by causing the device to shift to the testing mode without using terminals dedicated to testing. Besides, a shift to the connection testing mode by activation due to an erroneous operation or power-supply noise is prevented from occurring. In another semiconductor memory device the conversion circuit receives parallel testing patterns via a plurality of input terminals and converts the patterns into serial output patterns. Since the parallel testing patterns are converted into serial output patterns, connection testing can be performed even when the number of output terminals is small. Furthermore, another semiconductor memory device comprises an operation circuit and a conversion circuit. The operation circuit receives parallel testing patterns via a plurality of input terminals, performs a logic operation, and outputs parallel operation result patterns. The conversion circuit receives the parallel operation result patterns and converts the patterns into serial output patterns. The converted output patterns are sequentially output from output terminals. The testing patterns fed to the conversion circuit by the operation circuit can be reduced. Accordingly, the output patterns become shorter, and testing time is reduced.

    摘要翻译： 半导体存储器件包括检测单元和检测单元。 当所述电源接通时，所述检测单元多次检测预定终端的状态，并且当所有检测结果显示预期值时激活测试单元。 设备通过激活测试单元而转换到连接测试模式，并执行预定的测试。 因此，可以通过使设备转移到测试模式而不使用专用于测试的终端来进行测试。 此外，防止由于错误的操作或电源噪声的激活而转换到连接测试模式。 在另一个半导体存储器件中，转换电路经由多个输入端子接收并行测试图案，并将该图案转换为串行输出模式。 由于将并行测试模式转换为串行输出模式，即使输出端子数量少，也可进行连接测试。 此外，另一半导体存储器件包括一个操作电路和一个转换电路。 操作电路通过多个输入端子接收并行测试模式，执行逻辑运算，并输出并行运算结果模式。 转换电路接收并行运算结果模式并将模式转换为串行输出模式。 转换的输出图形从输出端依次输出。 可以减少由操作电路馈送到转换电路的测试图案。 因此，输出模式变短，测试时间缩短。

    Nonvolatile memory with illegitimate read preventing capability
    2.
    发明授权
    Nonvolatile memory with illegitimate read preventing capability 有权
    具有非法读取防止功能的非易失性存储器

    公开(公告)号：US06320787B1

    公开(公告)日：2001-11-20

    申请号：US09572319

    申请日：2000-05-18

    申请人： Mitsutaka Ikeda

    发明人： Mitsutaka Ikeda

    IPC分类号： G11C1604

    CPC分类号： G11C16/22

    摘要： According to the present invention, access to a password area in a nonvolatile memory cannot be granted by simple supply of an address in a normal order. According to one preferable mode, for instance, a trap address is set in the password area so that reading information from the password area is permitted only when the password area is accessed without accessing the trap address, whereas when the password area is accessed through the trap address, information reading is inhibited, or meaningless data is output or the information in the password area is destroyed. According to another preferable mode, the order in which access is made to the password area can arbitrarily be set so that accessing the password area in this order alone can permit the password area to be read, whereas when access to the password area is made in a different order, information reading is inhibited, or meaningless data is output or the information in the password area is destroyed. According to both modes, while the recording medium where the trap address or accessing order information is stored is a nonvolatile memory, it is constructed in such a manner that writing and reading are both prohibited. This invention can make it harder to gain access to a password area which is used to protect against illegitimate copying and can provide a nonvolatile memory having a stronger copy protection capability.

    摘要翻译： 根据本发明，不能通过以正常顺序简单地提供地址来对非易失性存储器中的密码区域进行访问。 根据一个优选模式，例如，在密码区域中设置陷阱地址，使得只有当访问密码区域而不访问陷阱地址时才允许从密码区域读取信息，而当通过密码区域访问密码区域时， 陷阱地址，信息读取被禁止或无意义的数据输出或密码区域中的信息被破坏。 根据另一优选方式，可以任意地设定对密码区域进行访问的顺序，以使得仅按此顺序访问密码区域可以允许读取密码区域，而在对密码区域进行访问时 不同的顺序，禁止信息读取，或输出无意义的数据，或密码区域中的信息被破坏。 根据这两种模式，当存储陷阱地址或访问命令信息的记录介质是非易失性存储器时，它被构造成使得写入和读取都被禁止。 本发明可以使得更难以访问用于防止非法复制的密码区域，并且可以提供具有更强的复制保护能力的非易失性存储器。

    Memory circuit having block address switching function
    6.
    发明授权
    Memory circuit having block address switching function 失效

    公开(公告)号：US06625071B2

    公开(公告)日：2003-09-23

    申请号：US10085065

    申请日：2002-03-01

    申请人： Mitsutaka Ikeda ,  Tsutomu Nakai ,  Koji Yamashita ,  Toshiyuki Kurita

    发明人： Mitsutaka Ikeda ,  Tsutomu Nakai ,  Koji Yamashita ,  Toshiyuki Kurita

    IPC分类号： G11C700

    CPC分类号： G11C29/76 ,  G11C29/88

    摘要： A memory circuit capable of salvaging defective cells, comprises a plurality of memory blocks each having a plurality of memory cells, a region which stores a block address of defective memory block that has defective cell, and a comparator circuit which compares the block address that is an object of access with the block address of the defective memory block, and detects access to the defective memory block, wherein in case where the comparator circuit detects access to the defective memory block, this defective memory block is replaced by the memory block that has the uppermost address (or lowermost address) among the plurality of memory blocks. In case where a plurality of defective memory blocks are present, the defective memory blocks are replaced with substitutive memory blocks having block addresses in order from the uppermost bit (or lowermost bit).

    Nonvolatile memory with illegitimate read preventing capability
    7.
    发明授权
    Nonvolatile memory with illegitimate read preventing capability 有权
    具有非法读取防止功能的非易失性存储器

    公开(公告)号：US06498748B2

    公开(公告)日：2002-12-24

    申请号：US09960509

    申请日：2001-09-24

    申请人： Mitsutaka Ikeda

    发明人： Mitsutaka Ikeda

    IPC分类号： G11C1604

    CPC分类号： G11C16/22

    摘要： According to the present invention, access to a password area in a nonvolatile memory cannot be granted by simple supply of an address in a normal order. According to one preferable mode, for instance, a trap address is set in the password area so that reading information from the password area is permitted only when the password area is accessed without accessing the trap address, whereas when the password area is accessed the trap address, whereas when the password area is access through the trap address, information reading is inhibited, or meaningless data is output or the information in the password area is destroyed. This invention can make it harder to gain access to a password area which is used to protect against illegitimate copying and can provide a nonvolatile memory having a stronger copy protection capability.

    摘要翻译： 根据本发明，不能通过以正常顺序简单地提供地址来对非易失性存储器中的密码区域进行访问。 根据一个优选模式，例如，在密码区域中设置陷阱地址，使得只有在访问密码区域而不访问陷阱地址的情况下才允许从密码区域读取信息，而当密码区域被访问时，陷阱 地址，而当密码区域通过陷阱地址访问时，禁止信息读取或输出无意义的数据或密码区域中的信息被破坏。 本发明可以使得更难以访问用于防止非法复制的密码区域，并且可以提供具有更强的复制保护能力的非易失性存储器。