公开(公告)号：US06208571B1

公开(公告)日：2001-03-27

申请号：US09500467

申请日：2000-02-09

申请人： Mitsutaka Ikeda ,  Tsutomu Taniguchi ,  Yoshikazu Homma

发明人： Mitsutaka Ikeda ,  Tsutomu Taniguchi ,  Yoshikazu Homma

IPC分类号： G11C700

CPC分类号： G01R31/31717 ,  G01R31/2853 ,  G01R31/31701 ,  G01R31/31905

摘要： A semiconductor memory device comprises a detecting unit and a testing unit. The detecting unit detects a plurality of times a state of a predetermined terminal when the power is switched on, and activates the testing unit when all results of the detections show expected values. The device shifts to a connection testing mode by activation of the testing unit, and performs predetermined testing. Therefore, the testing can be performed by causing the device to shift to the testing mode without using terminals dedicated to testing. Besides, a shift to the connection testing mode by activation due to an erroneous operation or power-supply noise is prevented from occurring. In another semiconductor memory device the conversion circuit receives parallel testing patterns via a plurality of input terminals and converts the patterns into serial output patterns. Since the parallel testing patterns are converted into serial output patterns, connection testing can be performed even when the number of output terminals is small. Furthermore, another semiconductor memory device comprises an operation circuit and a conversion circuit. The operation circuit receives parallel testing patterns via a plurality of input terminals, performs a logic operation, and outputs parallel operation result patterns. The conversion circuit receives the parallel operation result patterns and converts the patterns into serial output patterns. The converted output patterns are sequentially output from output terminals. The testing patterns fed to the conversion circuit by the operation circuit can be reduced. Accordingly, the output patterns become shorter, and testing time is reduced.

摘要翻译： 半导体存储器件包括检测单元和检测单元。 当所述电源接通时，所述检测单元多次检测预定终端的状态，并且当所有检测结果显示预期值时激活测试单元。 设备通过激活测试单元而转换到连接测试模式，并执行预定的测试。 因此，可以通过使设备转移到测试模式而不使用专用于测试的终端来进行测试。 此外，防止由于错误的操作或电源噪声的激活而转换到连接测试模式。 在另一个半导体存储器件中，转换电路经由多个输入端子接收并行测试图案，并将该图案转换为串行输出模式。 由于将并行测试模式转换为串行输出模式，即使输出端子数量少，也可进行连接测试。 此外，另一半导体存储器件包括一个操作电路和一个转换电路。 操作电路通过多个输入端子接收并行测试模式，执行逻辑运算，并输出并行运算结果模式。 转换电路接收并行运算结果模式并将模式转换为串行输出模式。 转换的输出图形从输出端依次输出。 可以减少由操作电路馈送到转换电路的测试图案。 因此，输出模式变短，测试时间缩短。

公开(公告)号：US06430090B1

公开(公告)日：2002-08-06

申请号：US09746072

申请日：2000-12-26

申请人： Yoshikazu Homma

发明人： Yoshikazu Homma

IPC分类号： G11C700

CPC分类号： G11C16/28 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/30 ,  G11C2211/5634

摘要： It is judged whether or not the output voltages of a memory cell and a first reference cell, which is for outputting a voltage at a first reference level to be compared with the output voltage of the memory cell, have reached their respective comparable levels, on the basis of the output voltages of first to third reference cells. After voltage values which can be compared with each other are obtained, the comparison result of the output voltage of the memory cell with the output voltage of the first reference cell is stored in a first latch circuit as the stored data of the memory cell, and the data is output via an output buffer. Thus, even when a reduction of an internal power supply voltage occurs, the data stored in the memory cell can be properly output.

公开(公告)号：US20090090619A1

公开(公告)日：2009-04-09

申请号：US12122781

申请日：2008-05-19

申请人： Toru Takashima ,  Yoshikazu Homma

发明人： Toru Takashima ,  Yoshikazu Homma

IPC分类号： C23C14/00

CPC分类号： C23C14/32 ,  H01J37/32009 ,  H01J37/3233 ,  H01J37/32357

摘要： A thin-film deposition system has a vacuum chamber and a plasma generator. The plasma generator includes a case, a cathode disposed in the case, an anode assembly disposed at an end of the case, a discharge power supply for applying a discharge voltage between the cathode and the anode assembly, and a gas supply means for supplying a discharge gas into the case. Electrons within a first plasma produced in the case are extracted into the vacuum chamber according to the discharge voltage. An evaporated material in a gaseous state inside the vacuum chamber is irradiated with electrons emitted from the plasma generator to produce a second plasma. The potential at the anode assembly is controlled by anode potential-controlling means such that the electrons within the second plasma are directed at the plasma generator and the ions within the second plasma are directed at the substrate.

摘要翻译： 薄膜沉积系统具有真空室和等离子体发生器。 等离子体发生器包括壳体，设置在壳体中的阴极，设置在壳体的端部的阳极组件，用于在阴极和阳极组件之间施加放电电压的放电电源，以及用于提供 将气体排放到壳体内。 在这种情况下产生的第一等离子体内的电子根据放电电压被提取到真空室中。 在真空室内的气态蒸发材料被从等离子体发生器发射的电子照射以产生第二等离子体。 阳极组件处的电位由阳极电位控制装置控制，使得第二等离子体内的电子被引导到等离子体发生器，并且第二等离子体内的离子被引导到衬底。

公开(公告)号：US4766313A

公开(公告)日：1988-08-23

申请号：US20181

申请日：1987-02-26

申请人： Yoshikazu Homma ,  Yoshikazu Ishii

发明人： Yoshikazu Homma ,  Yoshikazu Ishii

IPC分类号： G01Q30/10 ,  G01Q30/16 ,  H01J37/252 ,  H01J49/24

CPC分类号： H01J49/24 ,  H01J37/252

摘要： An apparatus for quantitative secondary ion mass spectrometry comprising a sealed chamber for storing a sample containing a light impurity element which is to be analyzed, secondary ion generating means for bombarding a primary ion beam onto the sample so as to allow the sample to emit a secondary ion of the light element, and quantitative analyzing means for detecting the secondary ion so as to quantitatively analyze the light element contained in the sample. First evacuating means evacuates said sealed chamber to an ultrahigh vacuum during quantitative analysis. First cryopanel means is arranged to surround the sample, and first cooling means keeps said first cryopanel means at a cryogenic temperature during quantitative analysis so that said first cryopanel means adsorbs a gas present in said sealed chamber.

摘要翻译： 一种用于定量二次离子质谱的装置，包括用于存储包含待分析的轻杂质元素的样品的密封室，用于将一次离子束轰击到样品上以使样品发射次级的二次离子产生装置 以及用于检测二次离子以定量分析样品中所含的轻元素的定量分析装置。 在定量分析过程中，首先排空装置将所述密封室排出至超高真空。 第一冷冻板装置被布置成围绕样品，并且第一冷却装置在定量分析期间使所述第一冷冻板装置保持在低温温度，使得所述第一冷冻板装置吸附存在于所述密封室中的气体。

公开(公告)号：US07866278B2

公开(公告)日：2011-01-11

申请号：US12122781

申请日：2008-05-19

申请人： Toru Takashima ,  Yoshikazu Homma

发明人： Toru Takashima ,  Yoshikazu Homma

IPC分类号： C23C16/00 ,  C23C14/00 ,  C25B11/00 ,  C25B13/00

CPC分类号： C23C14/32 ,  H01J37/32009 ,  H01J37/3233 ,  H01J37/32357

摘要： A thin-film deposition system has a vacuum chamber and a plasma generator. The plasma generator includes a case, a cathode disposed in the case, an anode assembly disposed at an end of the case, a discharge power supply for applying a discharge voltage between the cathode and the anode assembly, and a gas supply means for supplying a discharge gas into the case. Electrons within a first plasma produced in the case are extracted into the vacuum chamber according to the discharge voltage. An evaporated material in a gaseous state inside the vacuum chamber is irradiated with electrons emitted from the plasma generator to produce a second plasma. The potential at the anode assembly is controlled by anode potential-controlling means such that the electrons within the second plasma are directed at the plasma generator and the ions within the second plasma are directed at the substrate.

摘要翻译： 薄膜沉积系统具有真空室和等离子体发生器。 等离子体发生器包括壳体，设置在壳体中的阴极，设置在壳体的端部的阳极组件，用于在阴极和阳极组件之间施加放电电压的放电电源，以及用于提供 将气体排放到壳体内。 在这种情况下产生的第一等离子体内的电子根据放电电压被提取到真空室中。 在真空室内的气态蒸发材料被从等离子体发生器发射的电子照射以产生第二等离子体。 阳极组件处的电位由阳极电位控制装置控制，使得第二等离子体内的电子被引导到等离子体发生器，并且第二等离子体内的离子被引导到衬底。

公开(公告)号：US06928000B2

公开(公告)日：2005-08-09

申请号：US10821840

申请日：2004-04-12

申请人： Yoshikazu Homma ,  Tetsuji Takeguchi

发明人： Yoshikazu Homma ,  Tetsuji Takeguchi

IPC分类号： G11C16/06 ,  G11C7/08 ,  G11C8/08 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C29/02

CPC分类号： G11C29/026 ,  G11C8/08 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1202

摘要： The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

摘要翻译： 本发明提供了一种高速执行高可靠性数据读取操作的半导体存储器件。 该半导体存储器件根据从连接到字线的存储单元读出的信号与连接到参考字的参考单元读出的信号的比较结果，读取存储在存储单元中的数据 线。 该半导体存储器件包括负载能力调整电路，其根据存储器单元与字线的连接的每个位置调整启动参考单元的栅极的定时。

公开(公告)号：US06735120B2

公开(公告)日：2004-05-11

申请号：US10345187

申请日：2003-01-16

申请人： Yoshikazu Homma ,  Tetsuji Takeguchi

发明人： Yoshikazu Homma ,  Tetsuji Takeguchi

IPC分类号： G11C1606

CPC分类号： G11C29/026 ,  G11C8/08 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1202

摘要： The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

摘要翻译： 本发明提供了一种高速执行高可靠性数据读取操作的半导体存储器件。 该半导体存储器件根据从连接到字线的存储单元读出的信号与连接到参考字的参考单元读出的信号的比较结果，读取存储在存储单元中的数据 线。 该半导体存储器件包括负载能力调整电路，其根据存储器单元与字线的连接的每个位置调整启动参考单元的栅极的定时。

公开(公告)号：US06532174B2

公开(公告)日：2003-03-11

申请号：US09739395

申请日：2000-12-19

申请人： Yoshikazu Homma ,  Tetsuji Takeguchi

发明人： Yoshikazu Homma ,  Tetsuji Takeguchi

IPC分类号： G11C1606

CPC分类号： G11C29/026 ,  G11C8/08 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1202

摘要： The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

摘要翻译： 本发明提供了一种高速执行高可靠性数据读取操作的半导体存储器件。 该半导体存储器件根据从连接到字线的存储单元读出的信号与连接到参考字的参考单元读出的信号的比较结果，读取存储在存储单元中的数据 线。 该半导体存储器件包括负载能力调整电路，其根据存储器单元与字线的连接的每个位置调整启动参考单元的栅极的定时。