利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

55 条记录 (耗时 0.034 秒)

    SELF-CALIBRATED THERMAL SENSORS OF AN INTEGRATED CIRCUIT DIE
    3.
    发明申请
    SELF-CALIBRATED THERMAL SENSORS OF AN INTEGRATED CIRCUIT DIE 有权
    集成电路的自校准热传感器

    公开(公告)号：US20140365156A1

    公开(公告)日：2014-12-11

    申请号：US13915453

    申请日：2013-06-11

    申请人： Mohamed A. Abdelmoneum ,  David E. Duarte ,  Gregory F. Taylor

    发明人： Mohamed A. Abdelmoneum ,  David E. Duarte ,  Gregory F. Taylor

    IPC分类号： G01K15/00

    CPC分类号： G01K15/005 ,  G01K7/00 ,  G01K7/32

    摘要： Embodiments of the present disclosure provide self-calibrated thermal sensors of an integrated circuit (IC) die and associated techniques and configurations. In one embodiment, a self-calibrating thermal sensing device includes a resonator configured to oscillate at a frequency corresponding with a temperature of circuitry of an integrated circuit (IC) die, wherein the resonator is thermally coupled with the circuitry and configured to operate in a first mode and a second mode and logic operatively coupled with the resonator, and configured to calculate a first temperature corresponding with a first frequency of the resonator in the first mode using a first equation, calculate a second temperature corresponding with a second frequency of the resonator in the second mode using a second equation, and add an offset to the first equation and the second equation based on a result of a comparison of the first temperature and the second temperature. Other embodiments may be described and/or claimed.

    摘要翻译： 本公开的实施例提供集成电路（IC）管芯的自校准热传感器以及相关技术和配置。 在一个实施例中，自校准热感测装置包括配置成以对应于集成电路（IC）管芯的电路的温度的频率振荡的谐振器，其中谐振器与电路热耦合并且被配置为在 第一模式和第二模式以及与谐振器可操作地耦合的逻辑，并且被配置为使用第一等式计算与第一模式中的谐振器的第一频率相对应的第一温度，计算对应于谐振器的第二频率的第二温度 在第二模式中使用第二等式，并且基于第一温度和第二温度的比较的结果，向第一等式和第二等式添加偏移。 可以描述和/或要求保护其他实施例。

    Fuse cell array with redundancy features
    4.
    发明申请
    Fuse cell array with redundancy features 有权
    具有冗余特性的保险丝座阵列

    公开(公告)号：US20080151593A1

    公开(公告)日：2008-06-26

    申请号：US11644381

    申请日：2006-12-22

    申请人： Zhanping Chen ,  Jonathan P. Douglas ,  Praveen Mosalikanti ,  Kevin Zhang ,  Gregory F. Taylor

    发明人： Zhanping Chen ,  Jonathan P. Douglas ,  Praveen Mosalikanti ,  Kevin Zhang ,  Gregory F. Taylor

    IPC分类号： G11C17/16

    CPC分类号： G11C17/16 ,  G11C17/14 ,  G11C17/18 ,  G11C29/816

    摘要： An apparatus, a method, and a system for a fuse cell array are disclosed herein. A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are redundantly programmed. A sense amplifier is coupled to the plurality of fuse cells to read the pair of voltage outputs from each of the plurality of fuse cells, respectively. A comparator circuit is coupled to the sense amplifier to compare the pair of voltage outputs for each of the plurality of fuse cells and to output the compared result.

    摘要翻译： 本文公开了一种用于熔丝单元阵列的装置，方法和系统。 多个熔丝单元被布置成阵列。 一个或多个保险丝单元包括分别输出一对电压的一对熔丝器件，其中该对熔丝器件被冗余编程。 感测放大器耦合到多个熔丝单元以分别从多个熔丝单元中的每一个读出一对电压输出。 比较器电路耦合到读出放大器以比较多个熔丝单元中的每一个的一对电压输出并输出比较结果。

    Method and apparatus for voltage-mode differential simultaneous bi-directional signaling
    6.
    发明授权
    Method and apparatus for voltage-mode differential simultaneous bi-directional signaling 有权
    用于电压模式差分同步双向信令的方法和装置

    公开(公告)号：US06573764B1

    公开(公告)日：2003-06-03

    申请号：US09963037

    申请日：2001-09-24

    申请人： Gregory F. Taylor

    发明人： Gregory F. Taylor

    IPC分类号： H03K190175

    CPC分类号： H04L25/0292 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/085

    摘要： A driver/receiver circuit for use at one end of a simultaneous bi-directional differential signal line while being driven at the other end by a similar circuit. The driver/receiver circuit includes a differential driver, a differential receiver, an isolation circuit and an offset generator. The differential driver drives differential signal lines as a function of an output signal. The differential amplifier detects the differential voltage across the differential signal lines via the isolation circuit. The offset generator circuit receives the output signal and, in response, adds an offset to the input terminals of the differential amplifier. The offset cancels at least a portion of the differential voltage across the input terminals of the differential amplifier that results from the DOUT signal. The isolation circuit prevents the offset from significantly affecting the voltage across the differential signal lines.

    摘要翻译： 在同时双向差分信号线的一端使用的驱动器/接收器电路，同时在另一端由相似的电路驱动。 驱动器/接收器电路包括差分驱动器，差分接收器，隔离电路和偏移发生器。 差分驱动器驱动差分信号线作为输出信号的函数。 差分放大器通过隔离电路检测差分信号线两端的差分电压。 偏移发生器电路接收输出信号，作为响应，向差分放大器的输入端添加偏移。 该偏移抵消由DOUT信号产生的差分放大器的输入端上的差分电压的至少一部分。 隔离电路防止偏移显着影响差分信号线两端的电压。

    Internal clock jitter detector
    7.
    发明授权
    Internal clock jitter detector 有权
    内部时钟抖动检测器

    公开(公告)号：US06208169B1

    公开(公告)日：2001-03-27

    申请号：US09340975

    申请日：1999-06-28

    申请人： Keng L. Wong ,  Gregory F. Taylor ,  Ravishankar Kuppuswamy ,  Douglas R. Parker ,  Hung-Piao Ma ,  Kent R. Callahan ,  Xia Dai

    发明人： Keng L. Wong ,  Gregory F. Taylor ,  Ravishankar Kuppuswamy ,  Douglas R. Parker ,  Hung-Piao Ma ,  Kent R. Callahan ,  Xia Dai

    IPC分类号： H03K19096

    CPC分类号： H03L7/091 ,  H03L7/0814

    摘要： An apparatus and method for detecting and measuring internal clock jitter is disclosed. In one embodiment, a reference clock generator generates a reference clock signal based on an instantaneous clock signal. The reference clock signal includes the instantaneous clock signal delayed for an average duration. A phase comparing element receives both the instantaneous clock signal and the reference clock signal such that the phase comparing element measures a phase difference between the instantaneous clock signal and the reference clock signal. The magnitude and direction of the phase difference is indicated by one of a number of distinct phase difference bins in the phase comparing element.

    摘要翻译： 公开了一种用于检测和测量内部时钟抖动的装置和方法。 在一个实施例中，参考时钟发生器基于瞬时时钟信号产生参考时钟信号。 参考时钟信号包括延迟平均持续时间的瞬时时钟信号。 相位比较元件接收瞬时时钟信号和参考时钟信号，使得相位比较元件测量瞬时时钟信号和参考时钟信号之间的相位差。 相位差的幅度和方向由相位比较元件中的多个不同的相位差区之一表示。

    Semiconductor package substrate with power die
    8.
    发明授权
    Semiconductor package substrate with power die 失效
    半导体封装基板带电源模具

    公开(公告)号：US6075285A

    公开(公告)日：2000-06-13

    申请号：US990705

    申请日：1997-12-15

    申请人： Gregory F. Taylor ,  George L. Geannopoulos ,  Larry E. Mosley

    发明人： Gregory F. Taylor ,  George L. Geannopoulos ,  Larry E. Mosley

    IPC分类号： H01L23/498 ,  H01L23/64 ,  H05K1/02 ,  H01L23/52

    CPC分类号： H05K1/0231 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/642 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K2201/10545 ,  H05K2201/10734

    摘要： An apparatus that efficiently delivers electrical power and lowers the inductance to an integrated circuit. In one embodiment, the present invention includes an apparatus for delivering electrical power to an integrated circuit comprising two planes, substantially parallel to one another, having many ground and power traces. The ground and power traces of the separate planes are connected together and connected to the integrated circuit, thereby providing power to the integrated circuit. In each individual plane, the ground and power traces are substantially parallel to each other, one array of traces in one plane substantially perpendicular to another array of traces in another plane. The apparatus being electrically coupled to a printed circuit board having at least one decoupling capacitor with first and second electrodes coupled to at least two of the ground and power connections, respectively, of the integrated circuit through the printed circuit board, and the first and second ground and power planes.

    摘要翻译： 一种有效地传递电力并将电感降低到集成电路的装置。 在一个实施例中，本发明包括一种用于将电力传送到集成电路的装置，该集成电路包括彼此基本平行的两个平面，具有许多接地和功率迹线。 分立平面的接地和电源线连接在一起并连接到集成电路，从而为集成电路提供电源。 在每个单独的平面中，接地和功率迹线基本上彼此平行，一个平面中的一个迹线阵列基本上垂直于另一个平面中的另一个迹线阵列。 所述装置电耦合到具有至少一个去耦电容器的印刷电路板，所述去耦电容器具有分别通过印刷电路板耦合到集成电路的至少两个接地和电源连接的第一和第二电极，以及第一和第二电极 地面和电力飞机。

    Large fan-in, dynamic, bicmos logic gate
    9.
    发明授权
    Large fan-in, dynamic, bicmos logic gate 失效
    大型扇形，动态，双向逻辑门

    公开(公告)号：US5399918A

    公开(公告)日：1995-03-21

    申请号：US129664

    申请日：1993-09-30

    申请人： Gregory F. Taylor ,  Lawrence T. Clark

    发明人： Gregory F. Taylor ,  Lawrence T. Clark

    IPC分类号： G06F15/78 ,  H03K19/003 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02 ,  H03K17/16

    CPC分类号： H03K19/00346 ,  H03K19/09448

    摘要： A highly reliable, large fan-in, high speed, BiCMOS circuit. The amount of MOS transistor parasitic capacitance appearing on the output line of the circuit is reduced by adding only emitter capacitance of bipolar transistors to the output line for each input to the basic logic circuit. Circuitry is provided to raise the base voltage of a reverse biased bipolar transistors to reduce or eliminate the reverse bias.

    摘要翻译： 高可靠性，大型风扇，高速BiCMOS电路。 通过向基本逻辑电路的每个输入添加双极晶体管的发射极电容，减少了出现在电路的输出线上的MOS晶体管寄生电容的量。 提供电路以提高反向偏置双极晶体管的基极电压，以减少或消除反向偏置。

    On-chip frequency degradation compensation
    10.
    发明授权
    On-chip frequency degradation compensation 有权

    公开(公告)号：US07282937B2

    公开(公告)日：2007-10-16

    申请号：US10751132

    申请日：2003-12-31

    申请人： Ravisangar Muniandy ,  Gregory F. Taylor ,  Payman Aminzadeh

    发明人： Ravisangar Muniandy ,  Gregory F. Taylor ,  Payman Aminzadeh

    IPC分类号： G01R31/26

    CPC分类号： G06F1/04

    摘要： Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.