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1.发明授权Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last 有权首先通过对准通孔/电介质接合的三维集成电路集成，最后通过通孔形成公开(公告)号：US08563403B1
公开(公告)日：2013-10-22
申请号：US13534067
申请日：2012-06-27
IPC分类号： H01L21/30 , H01L21/46 , H01L21/8238 , H01L21/20
CPC分类号： H01L21/8221 , H01L21/76898 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05078 , H01L2224/05567 , H01L2224/05624 , H01L2224/06181 , H01L2224/08146 , H01L2224/2919 , H01L2224/32145 , H01L2224/80006 , H01L2224/80129 , H01L2224/80896 , H01L2224/83005 , H01L2224/8313 , H01L2224/8385 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2224/83 , H01L2224/80 , H01L2924/00 , H01L2224/05552 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A method includes forming a first integrated circuit (IC) device having a first substrate, an alignment via defined in the first substrate, a first wiring layer over the alignment via, and a first bonding layer over the first wiring layer; forming a second IC device having a second substrate, a second wiring layer over the second substrate, and a second bonding layer over the second wiring layer; bonding the first bonding layer of first IC device to the second bonding layer of second IC device; thinning a backside of the first IC device so as to expose the alignment via; and using the exposed alignment via to form a deep, through substrate via (TSV) that passes through the first IC device, through a bonding interface between the first IC device and second IC device, and landing on the second wiring layer of the second IC device.
摘要翻译： 一种方法包括形成具有第一衬底的第一集成电路（IC）器件，在第一衬底中限定的对准通孔，在对准通孔上方的第一布线层和在第一布线层上的第一接合层; 形成具有第二基板的第二IC器件，在所述第二基板上的第二布线层，以及在所述第二布线层上的第二接合层; 将第一IC器件的第一接合层接合到第二IC器件的第二接合层; 减薄第一IC器件的背面以暴露对准通孔; 以及使用所述暴露的取向通孔，通过所述第一IC器件通过所述第一IC器件和所述第二IC器件之间的接合界面形成穿过所述第一IC器件的深穿通衬底通孔（TSV），并且在所述第二IC器件的第二布线层上着陆 设备。
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公开(公告)号：US09214435B2
公开(公告)日：2015-12-15
申请号：US13476056
申请日：2012-05-21
IPC分类号： H01L21/768 , H01L23/00 , H01L23/48 , H01L25/065 , H01L23/538 , H01L27/06
CPC分类号： H01L24/09 , H01L21/76898 , H01L23/481 , H01L23/5386 , H01L24/80 , H01L24/82 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L27/0688 , H01L2224/02205 , H01L2224/08145 , H01L2224/0905 , H01L2224/80896 , H01L2224/82031 , H01L2224/82101 , H01L2224/9202 , H01L2224/94 , H01L2225/06544 , H01L2924/0002 , H01L2924/14 , H01L2924/3701 , H01L2924/00 , H01L2224/80
摘要： Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.
摘要翻译： 公开了结合三维积分的电路及其制造方法。 一个电路包括底层和多个上层。 底层包括连接到底层中的功能部件的底部着陆垫。 此外，上层堆叠在底层上方。 每个上层包括相应的上层板，其连接到各个上层中的各个功能部件。 着陆焊盘通过单个导电通孔耦合，并且在底层和上层的堆叠中对准，使得每个着陆焊盘从堆叠中的相邻层中的任何一个着陆焊盘偏移至少一个 预定金额。
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公开(公告)号：US20130307160A1
公开(公告)日：2013-11-21
申请号：US13476056
申请日：2012-05-21
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L24/09 , H01L21/76898 , H01L23/481 , H01L23/5386 , H01L24/80 , H01L24/82 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L27/0688 , H01L2224/02205 , H01L2224/08145 , H01L2224/0905 , H01L2224/80896 , H01L2224/82031 , H01L2224/82101 , H01L2224/9202 , H01L2224/94 , H01L2225/06544 , H01L2924/0002 , H01L2924/14 , H01L2924/3701 , H01L2924/00 , H01L2224/80
摘要： Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.
摘要翻译： 公开了结合三维积分的电路及其制造方法。 一个电路包括底层和多个上层。 底层包括连接到底层中的功能部件的底部着陆垫。 此外，上层堆叠在底层上方。 每个上层包括相应的上层板，其连接到各个上层中的各个功能部件。 着陆焊盘通过单个导电通孔耦合，并且在底层和上层的堆叠中对准，使得每个着陆焊盘从堆叠中的相邻层中的任何一个着陆焊盘偏移至少一个 预定金额。
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公开(公告)号：US20130328174A1
公开(公告)日：2013-12-12
申请号：US13489861
申请日：2012-06-06
CPC分类号： H01L25/50 , H01L23/562 , H01L25/0657 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.
摘要翻译： 边缘保护键合半导体晶片的方法。 第二半导体晶片和第一半导体晶片通过接合层/界面附着，并且第二半导体晶片进行变薄处理。 作为稀化过程的一部分，第一保护层被施加到第二和第一半导体晶片的边缘。 第三半导体晶片通过接合层/界面附接到第二半导体晶片，并且第三半导体晶片经历变薄处理。 作为稀化过程的一部分，第二保护层被施加到第三半导体晶片的边缘并且在第一保护层上。 第一，第二和第三半导体晶片形成晶片叠层。 晶片堆叠被切成多个3D芯片，同时保持第一和第二保护层。
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公开(公告)号：US08765578B2
公开(公告)日：2014-07-01
申请号：US13489861
申请日：2012-06-06
IPC分类号： H01L21/30
CPC分类号： H01L25/50 , H01L23/562 , H01L25/0657 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.
摘要翻译： 边缘保护键合半导体晶片的方法。 第二半导体晶片和第一半导体晶片通过接合层/界面附着，并且第二半导体晶片进行变薄处理。 作为稀化过程的一部分，第一保护层被施加到第二和第一半导体晶片的边缘。 第三半导体晶片通过接合层/界面附接到第二半导体晶片，并且第三半导体晶片经历变薄处理。 作为稀化过程的一部分，第二保护层被施加到第三半导体晶片的边缘并且在第一保护层上。 第一，第二和第三半导体晶片形成晶片叠层。 晶片堆叠被切成多个3D芯片，同时保持第一和第二保护层。
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6.发明授权Process of monitoring dispensing of process fluids in precision processing operations 有权在精密加工操作中监控过程流体的分配过程公开(公告)号：US07909208B2
公开(公告)日：2011-03-22
申请号：US11947856
申请日：2007-11-30
申请人： Spyridon Skordas
发明人： Spyridon Skordas
IPC分类号： G01F11/00
摘要： A process of monitoring the dispensing of process fluids in precision processing operations. A precision measuring instrument measures a cumulative amount of a process fluid dispensed to at least one dispensing station and compares that amount with a predetermined amount. An alarm is provided to an operator when the cumulative actual required amount of process fluid dispensed after a preset number of dispensations differs from the cumulative predetermined dispensed amount of that fluid by more than a preset percentage.
摘要翻译： 在精密加工操作中监测过程流体分配的过程。 精密测量仪器测量分配到至少一个分配站的过程流体的累积量，并将该量与预定量进行比较。 当在预设数量的分配之后分配的过程流体的累计实际需要量与该流体的累积预定分配量不同于预设百分比时，向操作者提供报警。
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7.发明申请PROCESS OF MONITORING DISPENSING OF PROCESS FLUIDS IN PRECISION PROCESSING OPERATIONS 有权在精密加工操作中监测过程流体分配的过程公开(公告)号：US20090139451A1
公开(公告)日：2009-06-04
申请号：US11947856
申请日：2007-11-30
申请人： Spyridon Skordas
发明人： Spyridon Skordas
IPC分类号： C23C16/00
摘要： A process of monitoring the dispensing of process fluids in precision processing operations. A precision measuring instrument measures a cumulative amount of a process fluid dispensed to at least one dispensing station and compares that amount with a predetermined amount. An alarm is provided to an operator when the cumulative actual required amount of process fluid dispensed after a preset number of dispensations differs from the cumulative predetermined dispensed amount of that fluid by more than a preset percentage.
摘要翻译： 在精密加工操作中监测过程流体分配的过程。 精密测量仪器测量分配到至少一个分配站的过程流体的累积量，并将该量与预定量进行比较。 当在预设数量的分配之后分配的过程流体的累计实际需要量与该流体的累积预定分配量不同于预设百分比时，向操作者提供报警。
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公开(公告)号：US20120021609A1
公开(公告)日：2012-01-26
申请号：US12843123
申请日：2010-07-26
申请人： NITIN H. PARBHOO , Spyridon Skordas
发明人： NITIN H. PARBHOO , Spyridon Skordas
CPC分类号： B05D1/002 , B05D3/104 , H01L21/6715
摘要： Embodiments of the invention provide methods and systems for depositing a viscous material on a substrate surface. In one embodiment, the invention provides a method of depositing a viscous material on a substrate surface, the method comprising: applying a pre-wet material to a surface of a substrate; depositing a viscous material atop the pre-wet material; rotating the substrate about an axis to spread the viscous material along the surface of the substrate toward a substrate edge; and depositing additional pre-wet material in a path along the surface and adjacent the spreading viscous material.
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公开(公告)号：US08236705B2
公开(公告)日：2012-08-07
申请号：US12843123
申请日：2010-07-26
申请人： Nitin H. Parbhoo , Spyridon Skordas
发明人： Nitin H. Parbhoo , Spyridon Skordas
IPC分类号： H01L21/469
CPC分类号： B05D1/002 , B05D3/104 , H01L21/6715
摘要： Embodiments of the invention provide methods and systems for depositing a viscous material on a substrate surface. In one embodiment, the invention provides a method of depositing a viscous material on a substrate surface, the method comprising: applying a pre-wet material to a surface of a substrate; depositing a viscous material atop the pre-wet material; rotating the substrate about an axis to spread the viscous material along the surface of the substrate toward a substrate edge; and depositing additional pre-wet material in a path along the surface and adjacent the spreading viscous material.
摘要翻译： 本发明的实施例提供了用于在基材表面上沉积粘性材料的方法和系统。 在一个实施例中，本发明提供了一种在衬底表面上沉积粘性材料的方法，所述方法包括：将预湿材料施加到衬底的表面; 在预湿材料的顶部沉积粘性材料; 使基板围绕轴线旋转，以将粘性材料沿着基板的表面朝向基板边缘铺展; 并且在沿着表面并邻近铺展粘性材料的路径中沉积额外的预湿材料。
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公开(公告)号：US20120146175A1
公开(公告)日：2012-06-14
申请号：US12963715
申请日：2010-12-09
申请人： Nicolas Loubet , Qing Liu , Sanjay C. Mehta , Spyridon Skordas
发明人： Nicolas Loubet , Qing Liu , Sanjay C. Mehta , Spyridon Skordas
IPC分类号： H01L29/02 , H01L21/762
CPC分类号： H01L29/78603 , H01L21/02112 , H01L21/02274 , H01L21/0228 , H01L21/76224 , H01L21/7624 , H01L29/66772
摘要： An insulating region for a semiconductor wafer and a method of forming same. The insulating region can include a tri-layer structure of silicon oxide, boron nitride and silicon oxide. The insulating region may be used to insulate a semiconductor device layer from an underlying bulk semiconductor substrate. The insulating region can be formed by coating the sides of a very thin cavity with silicon oxide, and filling the remainder of the cavity between the silicon oxide regions with boron nitride.
摘要翻译： 半导体晶片的绝缘区域及其形成方法。 绝缘区域可以包括氧化硅，氮化硼和氧化硅的三层结构。 绝缘区域可以用于使半导体器件层与下面的体半导体衬底绝缘。 绝缘区域可以通过用氧化硅涂覆非常薄的腔体的侧面并且用氮化硼填充氧化硅区域之间的空腔的其余部分来形成。
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