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21 条记录 (耗时 0.034 秒)

    Edge protection of bonded wafers during wafer thinning
    1.
    发明授权
    Edge protection of bonded wafers during wafer thinning 有权
    晶圆薄化期间接合晶片的边缘保护

    公开(公告)号：US08765578B2

    公开(公告)日：2014-07-01

    申请号：US13489861

    申请日：2012-06-06

    申请人： Douglas C. La Tulipe, Jr. ,  Spyridon Skordas ,  Tuan A. Vo ,  Kevin R. Winstel

    发明人： Douglas C. La Tulipe, Jr. ,  Spyridon Skordas ,  Tuan A. Vo ,  Kevin R. Winstel

    IPC分类号： H01L21/30

    CPC分类号： H01L25/50 ,  H01L23/562 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.

    摘要翻译： 边缘保护键合半导体晶片的方法。 第二半导体晶片和第一半导体晶片通过接合层/界面附着，并且第二半导体晶片进行变薄处理。 作为稀化过程的一部分，第一保护层被施加到第二和第一半导体晶片的边缘。 第三半导体晶片通过接合层/界面附接到第二半导体晶片，并且第三半导体晶片经历变薄处理。 作为稀化过程的一部分，第二保护层被施加到第三半导体晶片的边缘并且在第一保护层上。 第一，第二和第三半导体晶片形成晶片叠层。 晶片堆叠被切成多个3D芯片，同时保持第一和第二保护层。

    Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
    2.
    发明授权
    Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias 有权
    使用超深通孔制造超深通孔和三维集成电路的方法

    公开(公告)号：US09318375B2

    公开(公告)日：2016-04-19

    申请号：US12540490

    申请日：2009-08-13

    申请人： Douglas C. La Tulipe, Jr. ,  Mark Todhunter Robson

    发明人： Douglas C. La Tulipe, Jr. ,  Mark Todhunter Robson

    IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L27/06

    CPC分类号： H01L21/76802 ,  H01L21/76804 ,  H01L27/0688 ,  H01L2224/80896 ,  H01L2224/9202

    摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

    摘要翻译： 通过多个电介质层开口形成高纵横比的方法，高纵横比导电通孔，形成三维集成电路的方法和三维集成电路。 所述方法包括形成至少四个电介质层的叠层，并且用对第二和第四电介质层选择性的工艺蚀刻第一和第三介电层，用对第一和第二电介质层选择的工艺蚀刻第二和第三介电层。 有利地，用于蚀刻第三介电层的工艺对第一介电层基本不具有选择性。

    Field-effect-transistor with self-aligned diffusion contact
    7.
    发明授权
    Field-effect-transistor with self-aligned diffusion contact 有权
    具有自对准扩散接触的场效应晶体管

    公开(公告)号：US08637358B1

    公开(公告)日：2014-01-28

    申请号：US13542003

    申请日：2012-07-05

    申请人： Charles William Koburger, III ,  Douglas C. La Tulipe, Jr.

    发明人： Charles William Koburger, III ,  Douglas C. La Tulipe, Jr.

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795

    摘要： Embodiments of the present invention provide a method of forming fin-type transistors having replace-gate electrodes with self-aligned diffusion contacts. The method includes forming one or more silicon fins on top of an oxide layer, the oxide layer being situated on top of a silicon donor wafer; forming one or more dummy gate electrodes crossing the one or more silicon fins; forming sidewall spacers next to sidewalls of the one or more dummy gate electrodes; removing one or more areas of the oxide layer thereby creating openings therein, the openings being self-aligned to edges of the one or more fins and edges of the sidewall spacers; forming an epitaxial silicon layer in the openings; removing the donor wafer; and siliciding at least a bottom portion of the epitaxial silicon layer. A semiconductor structure formed thereby is also provided.

    摘要翻译： 本发明的实施例提供了一种形成具有具有自对准扩散接触的替代栅电极的鳍式晶体管的方法。 该方法包括在氧化物层的顶部上形成一个或多个硅散热片，氧化物层位于硅供体晶片的顶部; 形成与所述一个或多个硅散热片交叉的一个或多个虚拟栅电极; 在所述一个或多个虚拟栅电极的侧壁旁边形成侧壁间隔物; 去除所述氧化物层的一个或多个区域，从而在其中形成开口，所述开口与所述侧壁间隔物的所述一个或多个翅片和边缘的边缘自对准; 在所述开口中形成外延硅层; 去除施主晶片; 并且至少硅化外延硅层的底部。 还提供了由此形成的半导体结构。

    Non-relaxed embedded stressors with solid source extension regions in CMOS devices
    8.
    发明授权
    Non-relaxed embedded stressors with solid source extension regions in CMOS devices 失效
    CMOS器件中具有固态源延伸区域的非轻松嵌入式应力源

    公开(公告)号：US08592270B2

    公开(公告)日：2013-11-26

    申请号：US13115314

    申请日：2011-05-25

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Douglas C. La Tulipe, Jr.

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Douglas C. La Tulipe, Jr.

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/823807

    摘要： A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.

    摘要翻译： 形成场效应晶体管（FET）器件的方法包括在衬底上形成图案化栅极结构; 在所述衬底上形成固体源掺杂剂材料，所述栅极结构的相邻侧壁间隔物; 在足以使来自固体源掺杂剂材料的掺杂剂在栅极结构下方的衬底内扩散并形成源极/漏极延伸区域的温度下进行退火工艺; 在形成源极/漏极延伸区之后，在与衬底相邻的衬底中形成相应于源极/漏极区的沟槽; 以及在所述沟槽中形成嵌入式半导体材料，以在所述栅极结构下面限定的所述衬底的沟道区域上产生应力。

    Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
    10.
    发明授权
    Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias 有权
    使用超深通孔制造超深通孔和三维集成电路的方法

    公开(公告)号：US07955967B2

    公开(公告)日：2011-06-07

    申请号：US12540457

    申请日：2009-08-13

    申请人： Douglas C. La Tulipe, Jr. ,  Mark Todhunter Robson

    发明人： Douglas C. La Tulipe, Jr. ,  Mark Todhunter Robson

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/0688 ,  H01L21/76804 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

    摘要翻译： 通过多个电介质层开口形成高纵横比的方法，高纵横比导电通孔，形成三维集成电路的方法和三维集成电路。 所述方法包括形成至少四个电介质层的叠层，并且用对第二和第四电介质层选择性的工艺蚀刻第一和第三电介质层，用对第一和第二电介质层选择的工艺蚀刻第二和第三电介质层。 有利地，用于蚀刻第三介电层的工艺对第一介电层基本不具有选择性。