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公开(公告)号：US20130328174A1
公开(公告)日：2013-12-12
申请号：US13489861
申请日：2012-06-06
CPC分类号： H01L25/50 , H01L23/562 , H01L25/0657 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.
摘要翻译： 边缘保护键合半导体晶片的方法。 第二半导体晶片和第一半导体晶片通过接合层/界面附着，并且第二半导体晶片进行变薄处理。 作为稀化过程的一部分，第一保护层被施加到第二和第一半导体晶片的边缘。 第三半导体晶片通过接合层/界面附接到第二半导体晶片，并且第三半导体晶片经历变薄处理。 作为稀化过程的一部分，第二保护层被施加到第三半导体晶片的边缘并且在第一保护层上。 第一，第二和第三半导体晶片形成晶片叠层。 晶片堆叠被切成多个3D芯片，同时保持第一和第二保护层。
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公开(公告)号：US08765578B2
公开(公告)日：2014-07-01
申请号：US13489861
申请日：2012-06-06
IPC分类号： H01L21/30
CPC分类号： H01L25/50 , H01L23/562 , H01L25/0657 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.
摘要翻译： 边缘保护键合半导体晶片的方法。 第二半导体晶片和第一半导体晶片通过接合层/界面附着，并且第二半导体晶片进行变薄处理。 作为稀化过程的一部分，第一保护层被施加到第二和第一半导体晶片的边缘。 第三半导体晶片通过接合层/界面附接到第二半导体晶片，并且第三半导体晶片经历变薄处理。 作为稀化过程的一部分，第二保护层被施加到第三半导体晶片的边缘并且在第一保护层上。 第一，第二和第三半导体晶片形成晶片叠层。 晶片堆叠被切成多个3D芯片，同时保持第一和第二保护层。
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公开(公告)号：US5541439A
公开(公告)日：1996-07-30
申请号：US341250
申请日：1994-11-17
IPC分类号： H01L27/082 , H01L23/58
CPC分类号： H01L27/0825
摘要： There is disclosed a layout of a high voltage Darlington pair in which a circular field plate is utilized for both high voltage transistors in order to reduce the layout area. In this layout, both transistors of a Darlington pair are circular transistors and they both have a common center. This enables both high voltage transistors to share one field plate ring and one collector ring.
摘要翻译： 公开了高压达林顿对的布局，其中圆形场板用于两个高压晶体管，以便减小布局面积。 在这种布局中，达林顿对的两个晶体管都是圆形晶体管，它们都具有共同的中心。 这使得高压晶体管能够共享一个场板环和一个集电环。
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公开(公告)号：US5349223A
公开(公告)日：1994-09-20
申请号：US166400
申请日：1993-12-14
CPC分类号： H01L29/404 , H01L29/7802 , H01L29/7809
摘要： A vertical transistor which is built in a substrate of a given first carrier type utilizing standard processes but which has a unique layout which facilitates high voltage, high current operation while still conserving space. The transistor is built utilizing a repeatable combination gate/source area that is built in the upper area of the substrate such that the remaining lower portion of the substrate underneath the combination gate/source area is the drain area of the transistor.
摘要翻译： 采用标准工艺制造的具有给定第一载体类型的衬底的垂直晶体管，其具有独特的布局，其有利于高电压，高电流操作同时仍然节省空间。 晶体管是利用内置在衬底的上部区域中的可重复组合栅极/源极区域构建的，使得在组合栅极/源极区域下方的衬底的剩余下部分是晶体管的漏极区域。
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公开(公告)号：US5328859A
公开(公告)日：1994-07-12
申请号：US357
申请日：1993-01-04
申请人： Tuan A. Vo , Mohamad M. Mojaradi
发明人： Tuan A. Vo , Mohamad M. Mojaradi
IPC分类号： H01L21/8238 , H01L29/08 , H01L21/265 , H01L29/70
CPC分类号： H01L21/8238 , H01L29/0804 , Y10S148/011
摘要： A high voltage bipolar transistor fabricated on a CMOS substrate without adding any additional process steps. During the CMOS n-well mask and implant steps an n-well is formed for the transistor. Next, during the CMOS field and deep boron implant steps a circular p-field is formed within the n-well. Finally, during the CMOS p+ mask and implant steps the p+ emitter is formed. The presence of the p-field between the emitter and n+ base provides high voltage protection.
摘要翻译： 制造在CMOS衬底上的高电压双极晶体管，而不需要增加任何额外的工艺步骤。 在CMOS n阱掩模和注入步骤期间，为晶体管形成n阱。 接下来，在CMOS场和深硼注入步骤期间，在n阱内形成圆形p场。 最后，在CMOS p +掩模和注入步骤期间，形成p +发射极。 发射极和n +基极之间的p场的存在提供高电压保护。
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公开(公告)号：US09054109B2
公开(公告)日：2015-06-09
申请号：US13482352
申请日：2012-05-29
申请人： Wei Lin , Son Nguyen , Vamsi Paruchuri , Tuan A. Vo
发明人： Wei Lin , Son Nguyen , Vamsi Paruchuri , Tuan A. Vo
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76829 , H01L21/76834 , H01L21/76888 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and then thermally treated. The treatment converts the metal oxide over the first dielectric to a metal silicate while the metal oxide over the first interconnect remains as a self-aligned protective layer. When a subsequent dielectric stack is formed and patterned, the protective layer acts as an etch stop, oxidation barrier and ion bombardment protector. The protective layer is then removed from the patterned opening and a second interconnect formed. In a preferred embodiment the metal oxide is a manganese oxide and the metal silicate is a MnSiCOH, the interconnects are substantially copper and the dielectric contains ultra low-k.
摘要翻译： 从而形成减少的腐蚀互连结构和结构的方法。 具有减少的腐蚀的微电子互连的制造方法从具有第一电介质和第一互连的镶嵌结构开始。 金属氧化物层选择性沉积在金属或非选择性的镶嵌结构上，然后进行热处理。 处理将第一电介质上的金属氧化物转化为金属硅酸盐，同时第一互连上的金属氧化物保持为自对准保护层。 当形成并图案化后续的电介质堆叠时，保护层起蚀刻停止，氧化屏障和离子轰击保护的作用。 然后从图案化的开口去除保护层，形成第二互连。 在优选的实施方案中，金属氧化物是氧化锰，金属硅酸盐是MnSiCOH，互连基本上是铜，并且电介质包含超低k。
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公开(公告)号：US08691687B2
公开(公告)日：2014-04-08
申请号：US12683465
申请日：2010-01-07
CPC分类号： H01L21/2885 , H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L23/485 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.
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公开(公告)号：US20120236378A1
公开(公告)日：2012-09-20
申请号：US13235188
申请日：2011-09-16
申请人： Adrian Stoica , David Zhu , Mohammad Mehdi Mojarradi , Tuan A. Vo
发明人： Adrian Stoica , David Zhu , Mohammad Mehdi Mojarradi , Tuan A. Vo
CPC分类号： H03K19/0002 , G06F7/00 , G06F7/49 , H03K19/08
摘要： Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described.
摘要翻译： 使用N个大于2的N逻辑状态电平进行操作的电子逻辑门，以及操作这些门的方法。 电子逻辑门根据真值表进行操作。 至少两个具有可超过两个以上逻辑状态的逻辑状态的输入信号被提供给逻辑门。 每个逻辑门提供可以具有N个逻辑状态之一的输出信号。 所描述的门的示例包括具有两个输入A和B的NAND / NAND门和具有三个输入A，B和C的NAND / NAND门，其中A，B和C可以采取四种逻辑状态中的任一种。 描述使用这种门的系统，并且说明它们的操作。 还描述了使用N个逻辑状态级操作的光逻辑门。
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9.发明申请SELF-ALIGNED COMPOSITE M-MOx/DIELECTRIC CAP FOR Cu INTERCONNECT STRUCTURES 有权用于Cu互连结构的自对准复合材料M-MOx /电介质盖公开(公告)号：US20110162874A1
公开(公告)日：2011-07-07
申请号：US12683590
申请日：2010-01-07
CPC分类号： H01L21/76849 , H01L21/76846 , H01L21/76864 , H01L21/76867
摘要： An interconnect structure is provided that has improved electromigration resistance as well as methods of forming such an interconnect structure. The interconnect structure includes an interconnect dielectric material having a dielectric constant of about 4.0 or less. The interconnect dielectric material has at least one opening therein that is filled with a Cu-containing material. The Cu-containing material within the at least one opening has an exposed upper surface that is co-planar with an upper surface of the interconnect dielectric material. The interconnect structure further includes a composite M-MOx cap located at least on the upper surface of the Cu-containing material within the at least one opening. The composite M-MOx cap includes an upper region that is composed of the metal having a higher affinity for oxygen than copper and copper oxide and a lower region that is composed of a non-stoichiometric oxide of said metal. The interconnect structure further includes a dielectric cap located on at least an upper surface of the composite M-MOx cap.
摘要翻译： 提供了具有改进的电迁移阻力的互连结构以及形成这种互连结构的方法。 互连结构包括具有约4.0或更小的介电常数的互连电介质材料。 互连电介质材料在其中具有填充有含Cu材料的至少一个开口。 至少一个开口内的含Cu材料具有与互连电介质材料的上表面共面的暴露的上表面。 互连结构还包括至少位于至少一个开口内的含Cu材料的上表面上的复合M-MOx帽。 复合M-MOx帽包括由与氧和氧化铜相比具有比氧更高的亲和性的金属构成的上部区域和由所述金属的非化学计量氧化物构成的下部区域。 互连结构还包括位于复合M-MOx帽的至少上表面上的介电帽。
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10.发明授权Advanced technique for packaging multiple number of electrically stackable high voltage transistors in one package 失效在一个封装中封装多个可电叠置的高压晶体管的先进技术
公开(公告)号：US5577617A
公开(公告)日：1996-11-26
申请号：US581385
申请日：1995-12-29
IPC分类号： H01L23/495 , B65D73/02
CPC分类号： H01L23/49575 , H01L2924/0002
摘要： High voltage circuitry often requires assembling an array of high voltage devices that are electrically isolated from one another. A lead frame that fits within conventional plastic packaging has been designed that will allow electrical isolation of the substrates of two or more transistors mounted together in a single package.
摘要翻译： 高电压电路通常需要组装彼此电隔离的高压器件阵列。 已经设计出适合传统塑料封装的引线框架，其将允许在单个封装中安装在一起的两个或多个晶体管的基板电隔离。
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