公开(公告)号：US5592004A

公开(公告)日：1997-01-07

申请号：US534976

申请日：1995-09-28

申请人： Muneo Tamura ,  Takeshi Yamauchi ,  Katuhide Niwa ,  Takeshi Fukazawa ,  Akira Kuroyanagi ,  Tooru Yamaoka

发明人： Muneo Tamura ,  Takeshi Yamauchi ,  Katuhide Niwa ,  Takeshi Fukazawa ,  Akira Kuroyanagi ,  Tooru Yamaoka

IPC分类号： H01L21/8247 ,  C23C16/34 ,  H01L21/314 ,  H01L21/318 ,  H01L23/31 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/06 ,  H01L29/78

CPC分类号： C23C16/347 ,  H01L21/3185 ,  H01L23/3171 ,  H01L2924/0002

摘要： A semiconductor device includes a semiconductor element. A silicon nitride film covers the semiconductor element. The silicon nitride film is made of Si.sub.X N.sub.Y H.sub.Z, where X, Y, and Z denote atomic fractions of Si, N, and H respectively. The silicon nitride film relates to an optical absorption edge wavelength shorter than 254 nm. A mean area of regions surrounded by crystal-like grain boundaries at a surface of the silicon nitride film is equal to 4.5.times.10.sup.4 nm.sup.2 or more. The semiconductor element may include a memory element from which information can be erased by exposure to ultraviolet rays.

摘要翻译： 半导体器件包括半导体元件。 氮化硅膜覆盖半导体元件。 氮化硅膜由SiXNYHZ制成，其中X，Y和Z分别表示Si，N和H的原子级分。 氮化硅膜涉及短于254nm的光吸收边缘波长。 在氮化硅膜表面的晶状晶界包围的区域的平均面积为4.5×10 4 nm 2以上。 半导体元件可以包括可通过暴露于紫外线而从其中擦除信息的存储元件。

公开(公告)号：US5877095A

公开(公告)日：1999-03-02

申请号：US698841

申请日：1996-08-16

申请人： Muneo Tamura ,  Takeshi Yamauchi ,  Katuhide Niwa ,  Takeshi Fukazawa ,  Akira Kuroyanagi

发明人： Muneo Tamura ,  Takeshi Yamauchi ,  Katuhide Niwa ,  Takeshi Fukazawa ,  Akira Kuroyanagi

IPC分类号： H01L21/8247 ,  C23C16/34 ,  H01L21/314 ,  H01L21/318 ,  H01L23/31 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/306

CPC分类号： C23C16/347 ,  H01L21/3185 ,  H01L23/3171 ,  H01L2924/0002

摘要： A semiconductor device includes a semiconductor element. A silicon nitride film covers the semiconductor element. The silicon nitride film is made of Si.sub.X N.sub.Y H.sub.Z, where X, Y, and Z denote atomic fractions of Si, N, and H resptively. The silicon nitride film relates to an optical absorption edge wavelength shorter than 254 nm. A mean area of regions surrounded by crystal-like grain boundaries at a surface of the silicon nitride film is equal to 4.5.times.10.sup.4 nm.sup.2 or more. The semiconductor element may include a memory element from which information can be erased by exposure to ultraviolet rays.

摘要翻译： 半导体器件包括半导体元件。 氮化硅膜覆盖半导体元件。 氮化硅膜由SiXNYHZ制成，其中X，Y和Z表示Si，N和H的原子级分。 氮化硅膜涉及短于254nm的光吸收边缘波长。 在氮化硅膜表面的晶状晶界包围的区域的平均面积为4.5×10 4 nm 2以上。 半导体元件可以包括可通过暴露于紫外线而从其中擦除信息的存储元件。

公开(公告)号：US07586151B2

公开(公告)日：2009-09-08

申请号：US11578949

申请日：2005-05-11

申请人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7811

摘要： The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.

摘要翻译： 本发明提供了一种绝缘栅半导体器件，其在沟槽底部附近具有浮动区域，并且能够可靠地实现高耐压。 绝缘栅半导体器件100包括电流流过的单元区域和围绕单元区域的端子区域。 半导体器件100还在单元区域中具有多个栅极沟槽21以及端子区域中的多个端子沟槽62。 栅极沟槽21形成为条状，并且端子沟槽62同心地形成。 在半导体器件100中，栅极沟槽21和端子沟槽62以栅极沟槽21的端部和端子沟槽62的侧面之间的间隔均匀的方式定位。 也就是说，栅极沟槽21的长度根据端子沟槽62的拐角的曲率来调节。

公开(公告)号：US20050202117A1

公开(公告)日：2005-09-15

申请号：US11079260

申请日：2005-03-14

申请人： Hidehisa Nasu ,  Akira Kuroyanagi ,  Masato Ichikawa ,  Akira Sahashi

发明人： Hidehisa Nasu ,  Akira Kuroyanagi ,  Masato Ichikawa ,  Akira Sahashi

IPC分类号： B29C45/26 ,  B29C45/00 ,  B29C45/14 ,  B29C45/72 ,  B29C65/70 ,  B29L23/00

CPC分类号： B29C45/0062 ,  B29C45/7207 ,  B29C65/103 ,  B29C65/42 ,  B29C65/542 ,  B29C66/0242 ,  B29C66/1312 ,  B29C66/547 ,  B29C2045/14877

摘要： The device includes: a runner block arranged at a position close to the injection port for resin material for secondary forming; and a slide core moved relatively with the runner block. In the runner block, a guide passage is formed which is communicated with a passage formed when pipe-shaped passages of the primary moldings are butted against each other. A heating medium passage or a resin material passage formed in the slide core are moved so that either the heating medium passage or the resin material passage can be selectively communicated with the guide passage formed in the runner block.

摘要翻译： 该装置包括：设置在靠近用于二次成型的树脂材料的注入口的位置处的流道块; 并且滑块与滑块相对移动。 在流道块中，形成一个引导通道，该引导通道与一次模制品的管状通道彼此对接时形成的通道连通。 移动形成在滑动芯体中的加热介质通道或树脂材料通道，使得加热介质通道或树脂材料通道可以与形成在流道块中的引导通道选择性地连通。

公开(公告)号：US06864532B2

公开(公告)日：2005-03-08

申请号：US10175294

申请日：2002-06-20

申请人： Takaaki Aoki ,  Akira Kuroyanagi ,  Mikimasa Suzuki ,  Takafumi Arakawa ,  Yukio Tsuzuki

发明人： Takaaki Aoki ,  Akira Kuroyanagi ,  Mikimasa Suzuki ,  Takafumi Arakawa ,  Yukio Tsuzuki

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/739 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L29/7813 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/7397

摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.

摘要翻译： 沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。 栅极绝缘膜包括位于沟槽的壁上的第一部分和位于沟槽的上部和底部的第二部分。 第一部分包括第一氧化膜，氮化物膜和第二氧化物膜。 第二部分仅包括氧化膜并且比第一部分厚。 因此，可以减小沟槽的上下角部的电场集中以提高耐压。 此外，沟槽的端部可以具有比第一部分更厚的绝缘层。

公开(公告)号：US06373093B1

公开(公告)日：2002-04-16

申请号：US09776769

申请日：2001-02-06

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

IPC分类号： H01L2976

摘要： A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

公开(公告)号：US5462896A

公开(公告)日：1995-10-31

申请号：US903465

申请日：1992-06-23

申请人： Atushi Komura ,  Kenji Kondo ,  Akira Kuroyanagi

发明人： Atushi Komura ,  Kenji Kondo ,  Akira Kuroyanagi

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/336 ,  H01L29/78 ,  H01L21/465

CPC分类号： H01L29/66719 ,  H01L21/31116 ,  H01L29/66712 ,  H01L29/7811 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368

摘要： A method fabricates a semiconductor device having a sidewall made from an insulation film at each side of a gate electrode portion. The method forms a polysilicon gate electrode (11a) on a gate oxide film (10) in a predetermined region on an n.sup.- epitaxial layer (2). A CVD silicon oxide film (15) having a predetermined thickness is formed over the polysilicon gate electrode material (11a) on the n.sup.- epitaxial layer (2). A magnetron enhanced reactive ion etching apparatus is used to etch the CVD silicon oxide film (15) while pouring a CHF.sub.3 gas made by coupling carbon, hydrogen, and fluorine and an N.sub.2 gas onto the etched material, such that the CVD silicon oxide film (15) is left only at each side of the polysilicon gate electrode material (11a), to form a sidewall (16). To avoid electrodes of the magnetron enhanced reactive ion etching apparatus from staining, CHF.sub.3 /He/N.sub.2 /O.sub.2 may be used for etching.

摘要翻译： 一种制造半导体器件，其具有由栅电极部分的每一侧由绝缘膜制成的侧壁。 该方法在n型外延层（2）上的预定区域中的栅极氧化膜（10）上形成多晶硅栅电极（11a）。 在n外延层（2）上的多晶硅栅电极材料（11a）上形成具有预定厚度的CVD氧化硅膜（15）。 使用磁控增强反应离子蚀刻装置来蚀刻CVD氧化硅膜（15），同时将通过将碳，氢和氟与N 2气体偶合而形成的CHF 3气体倒入到蚀刻材料上，使得CVD氧化硅膜（ 15）仅留在多晶硅栅电极材料（11a）的每一侧，以形成侧壁（16）。 为了避免磁控管增强反应离子蚀刻装置的电极染色，可以使用CHF 3 / He / N 2 / O 2进行蚀刻。

公开(公告)号：US5410171A

公开(公告)日：1995-04-25

申请号：US038951

申请日：1993-03-29

申请人： Yasuaki Tsuzuki ,  Akira Kuroyanagi ,  Toshiaki Nishizawa

发明人： Yasuaki Tsuzuki ,  Akira Kuroyanagi ,  Toshiaki Nishizawa

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L27/02 ,  H01L27/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7815 ,  H01L27/0248 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095

摘要： A power DMOS semiconductor device providing improved current detection accuracy can be produced using standard pocessess. The device includes main wells, subwells and a line well which is independent of the main wells and subwells. These wells are formed by doping the surface of a semiconductor substrate with well-forming impurities. The line well surrounds the subwells at a predetermined distance away from the subwells to relax an electric field on the surface of the substrate. Gate electrodes are patterned to form a line opening which surrounds the subwells. The line opening serves as a mask when forming the line well by doping the surface of the substrate with the well-forming impurities. Accordingly, the width of a region between the line well and an adjacent subwell will not fluctuate.

摘要翻译： 提供提高电流检测精度的功率DMOS半导体器件可以使用标准的方式产生。 该装置包括主井，下井和一条独立于主井和下井的线井。 这些阱通过掺杂具有良好形成杂质的半导体衬底的表面而形成。 线路井在距离底孔预定距离处围绕底孔，以松弛基底表面上的电场。 图案化栅电极以形成围绕底孔的线路开口。 线形开口用于通过用形成阱的杂质掺杂衬底的表面来形成线状物时用作掩模。 因此，线槽与相邻的底座之间的区域的宽度不会波动。

公开(公告)号：US5063423A

公开(公告)日：1991-11-05

申请号：US567760

申请日：1990-08-15

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

IPC分类号： H01L21/28 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/7883

摘要： A tunnel insulating film of a three-layer structure, wherein an oxide film is interposed between nitrided oxide films, is formed on the surface of a semiconductor substrate. A first polysilicon film serving as a low-concentration impurity region is formed on the tunnel insulating film. An oxide film is formed on that region of the first polysilicon film, which corresponds to the tunnel insulating film, the oxide film having such a thickness that the film can serve as a stopper for impurity diffusion and can allow electrons to pass through. A second polysilicon film, having an impurity concentration higher than that of the first polysilicon film, is formed on the oxide film. The first and second polysilicon films constitute a floating gate. A third polysilicon film serving as a control gate is formed above the second polysilicon film, with an insulating layer interposed therebetween.

摘要翻译： 在半导体衬底的表面上形成三层结构的隧道绝缘膜，其中在氮化氧化物膜之间插入氧化膜。 在隧道绝缘膜上形成用作低浓度杂质区的第一多晶硅膜。 在第一多晶硅膜的与隧道绝缘膜相对应的区域上形成氧化膜，氧化膜具有使膜能够作为用于杂质扩散的阻挡层的厚度，并且可以使电子通过。 在氧化膜上形成杂质浓度高于第一多晶硅膜的第二多晶硅膜。 第一和第二多晶硅膜构成浮栅。 用作控制栅极的第三多晶硅膜形成在第二多晶硅膜上方，绝缘层位于其间。

公开(公告)号：US5017979A

公开(公告)日：1991-05-21

申请号：US344605

申请日：1989-04-28

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/7883

摘要： A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

摘要翻译： 在半导体衬底的表面上形成栅极氧化膜。 在对应于隧道区域的部分中形成厚度小于栅极绝缘膜厚度的隧道绝缘膜。 在栅极绝缘膜上形成杂质浓度低的第一硅膜。 在第一硅膜上形成杂质浓度高于第一硅膜的第二硅膜，以便与第一硅膜连接。 通过绝缘膜在第二硅膜上形成第三硅膜。 第二和第三硅膜分别形成浮动和控制栅极，从而形成半导体存储器件。