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公开(公告)号：US20240063224A1
公开(公告)日：2024-02-22
申请号：US18497020
申请日：2023-10-30
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Korekiyo ITO , Masatomi HARADA
CPC classification number: H01L27/1203 , H01G4/33 , H01L28/40 , H03H9/02125 , H03H9/02952 , H03H9/25 , H03H9/173 , H03H7/38 , H03H7/0115
Abstract: A support substrate for a passive electronic component, the support substrate including: a semiconductor substrate; a charge trap layer on the semiconductor substrate and having a higher crystal defect density than the semiconductor substrate; and an insulating layer on the charge trap layer. In a first aspect, the insulating layer is composed of silicon nitride, and an atomic concentration ratio of N to a total amount of Si and N in the insulating layer is not greater than 45 atom %. In a second aspect, the insulating layer includes a first insulating layer on the charge trap layer; and a second insulating layer on the first insulating layer, wherein a first fixed charge within the first insulating layer and a second fixed charge within the second insulating layer have opposite polarities, and the first insulating layer has a thickness of not less than 0.5 nm and not greater than 3 nm.
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公开(公告)号：US20210382123A1
公开(公告)日：2021-12-09
申请号：US17406128
申请日：2021-08-19
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masashi KUBOTA , Korekiyo ITO
Abstract: A magneto-resistive element includes a first element section including a first unit element and a second element section including a second unit element. The first element section is connected to the second element section in series. The first unit element includes a first reference layer with a magnetization that is fixed in an in-plane direction, and a first free layer including a vortex magnetization. The second unit element includes a second reference layer with a magnetization that is fixed in an in-plane direction, and a second free layer including a vortex magnetization. A direction of the fixed magnetization of the first reference layer is opposite to that of the second reference layer.
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公开(公告)号：US20240071687A1
公开(公告)日：2024-02-29
申请号：US18502512
申请日：2023-11-06
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Korekiyo ITO , Masatomi HARADA , Yuta IMAMURA
CPC classification number: H01G4/224 , H01G4/005 , H01G4/30 , H05K1/181 , H05K2201/10015
Abstract: A semiconductor device that includes: a substrate having a first main surface and a second main surface opposite to each other in a thickness direction; a circuit layer on the first main surface of the substrate, the circuit layer having a first electrode layer, a second electrode layer, a dielectric layer between the first electrode layer and the second electrode layer, a first outer electrode and a second outer electrode each extending to a surface of the circuit layer opposite to the substrate; and a first resin body at each of four corners of the substrate in a plan view in the thickness direction, and wherein, in the thickness direction, a top end of the first resin body on the side opposite to the substrate is positioned higher than top ends of the first outer electrode and the second outer electrode on the side opposite to the substrate.
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公开(公告)号：US20240062958A1
公开(公告)日：2024-02-22
申请号：US18497066
申请日：2023-10-30
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masatomi HARADA , Korekiyo ITO , Takeshi KAGAWA , Yuta IMAMURA
Abstract: A capacitor that includes: a substrate; a first electrode layer on the substrate, the first electrode layer including a first principal surface facing the substrate, and a second principal surface opposite the first principal surface; a dielectric film on the first electrode layer and covering an end portion of the first electrode layer; a second electrode layer on the dielectric film, the second electrode layer including a third principal surface facing the dielectric film, a fourth principal surface opposite the third principal surface, and a side surface joining the third principal surface and the fourth principal surface, wherein at least part of the side surface of the second electrode layer has a tapered shape which is inclined inward from the third principal surface to the fourth principal surface.
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公开(公告)号：US20170200882A1
公开(公告)日：2017-07-13
申请号：US15473661
申请日：2017-03-30
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Korekiyo ITO
IPC: H01L41/253 , H01L21/02 , H01L41/08 , H01L41/332 , H01L41/18 , H01L41/277 , H01L41/297 , H01L41/083 , H01L41/47
Abstract: In a method of manufacturing a piezoelectric device, during an isolation formation step, a supporting substrate has a piezoelectric thin film formed on its front with a compressive stress film present on its back. The compressive stress film compresses the surface on a piezoelectric single crystal substrate side of the supporting substrate, and the piezoelectric thin film compresses the back of the supporting substrate, which is opposite to the surface on the piezoelectric single crystal substrate side. Thus, the compressive stress produced by the compressive stress film and that produced by the piezoelectric thin film are balanced in the supporting substrate, which causes the supporting substrate to be free of warpage and remain flat. A driving force that induces isolation in the isolation formation step is gasification of the implanted ionized element rather than the compressive stress to the isolation plane produced by the piezoelectric thin film.
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Patent Agency Ranking
公开(公告)号：US20140055008A1
公开(公告)日：2014-02-27
申请号：US14071683
申请日：2013-11-05
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Korekiyo ITO
IPC: H01L41/053 , H03H9/05 , H01L41/18
CPC classification number: H01L41/053 , H01L41/18 , H01L41/313 , H03H3/02 , H03H3/08 , H03H9/02007 , H03H9/02574 , H03H9/05 , H03H2003/021 , Y10T29/42 , Y10T29/49126 , Y10T156/1153
Abstract: In a piezoelectric device and a method of manufacturing thereof, after an ion implanted portion is formed in a piezoelectric single crystal substrate by implantation of hydrogen ions, an interlayer of a metal is formed on a rear surface of the piezoelectric single crystal substrate. In addition, a support member is bonded to the piezoelectric single crystal substrate with the interlayer interposed therebetween. A composite piezoelectric body in which the ion implanted portion is formed is heated at about 450° C. to about 700° C. to oxidize the metal of the interlayer so as to decrease the conductivity thereof. Accordingly, the conductivity of the interlayer is decreased, so that a piezoelectric device having excellent resonance characteristics is provided.
Abstract translation: 在压电器件及其制造方法中，在通过注入氢离子在压电单晶衬底中形成离子注入部分之后，在压电单晶衬底的后表面上形成金属中间层。 此外，支撑构件与介于其间的夹层结合到压电单晶衬底。 其中形成离子注入部分的复合压电体在约450℃至约700℃下加热，以中间层的金属氧化，从而降低其导电性。 因此，中间层的导电性降低，提供了具有优异的谐振特性的压电元件。
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公开(公告)号：US20240072107A1
公开(公告)日：2024-02-29
申请号：US18502482
申请日：2023-11-06
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masatomi HARADA , Korekiyo ITO , Takeshi KAGAWA
CPC classification number: H01L28/60 , H01L23/564 , H03H7/0115 , H03H7/38
Abstract: A semiconductor device that includes a substrate; a first electrode layer on the substrate; a dielectric film on the first electrode layer; a second electrode layer on the dielectric film; a protective layer covering the first electrode layer and the second electrode layer; and an outer electrode penetrating the protective layer. The dielectric film includes silicon nitride, and an atomic concentration ratio of Si to a total amount of Si and N contained in the dielectric film is 43 atom % to 70 atom %.
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公开(公告)号：US20170062698A1
公开(公告)日：2017-03-02
申请号：US15348129
申请日：2016-11-10
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Korekiyo ITO , Takashi IWAMOTO
IPC: H01L41/29
Abstract: In a method of manufacturing a piezoelectric device, among a +C plane on a +Z axis side of a piezoelectric thin film and a −C plane on a −Z axis side of the piezoelectric thin film, the −C plane on the −Z axis side of the piezoelectric thin film is etched. Thus, −Z planes of the piezoelectric thin film on which epitaxial growth is possible are exposed. Ti is epitaxially grown on the −Z planes of the piezoelectric thin film in the −Z axis direction such that the crystal growth plane thereof is parallel to the −Z planes of the piezoelectric thin film. Al is then epitaxially grown on the surface of the Ti electrode in the −Z axis direction such that the crystal growth plane thereof is parallel to the −Z planes of the piezoelectric thin film.
Abstract translation: 在制造压电元件的方法中，在压电薄膜的+ Z轴侧的+ C平面和压电薄膜的-Z轴侧的-C面之间，-Z 蚀刻压电薄膜的轴侧。 因此，可以暴露外延生长的压电薄膜的-Z平面。 Ti在-Z轴方向上在压电薄膜的-Z平面上外延生长，使得其晶体生长面平行于压电薄膜的-Z平面。 然后在-Z轴方向上在Ti电极的表面上外延生长Al，使得其晶体生长面平行于压电薄膜的-Z平面。
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公开(公告)号：US20130307372A1
公开(公告)日：2013-11-21
申请号：US13850520
申请日：2013-03-26
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Korekiyo ITO
IPC: H01L41/27 , H01L41/053
CPC classification number: H01L41/253 , H01L21/02694 , H01L41/0536 , H01L41/081 , H01L41/0815 , H01L41/0838 , H01L41/18 , H01L41/27 , H01L41/277 , H01L41/297 , H01L41/312 , H01L41/332 , H01L41/47 , H03H3/02 , H03H3/08 , H03H9/02574 , H03H9/059 , H03H9/173
Abstract: In a method of manufacturing a piezoelectric device, during an isolation formation step, a supporting substrate has a piezoelectric thin film formed on its front with a compressive stress film present on its back. The compressive stress film compresses the surface on a piezoelectric single crystal substrate side of the supporting substrate, and the piezoelectric thin film compresses the back of the supporting substrate, which is opposite to the surface on the piezoelectric single crystal substrate side. Thus, the compressive stress produced by the compressive stress film and that produced by the piezoelectric thin film are balanced in the supporting substrate, which causes the supporting substrate to be free of warpage and remain flat. A driving force that induces isolation in the isolation formation step is gasification of the implanted ionized element rather than the compressive stress to the isolation plane produced by the piezoelectric thin film.
Abstract translation: 在压电元件的制造方法中，在隔离形成工序中，支撑基板的前面形成有压电薄膜，其背面存在压应力膜。 压缩应力膜压缩支撑基板的压电单晶基板侧的表面，压电薄膜压缩与压电单晶基板侧的表面相反的支撑基板的背面。 因此，压缩应力膜产生的压电应力和由压电薄膜产生的压缩应力在支撑基板上平衡，这导致支撑基板没有翘曲并保持平坦。 在隔离形成步骤中诱导隔离的驱动力是将植入的离子化元素气化，而不是由压电薄膜产生的隔离面的压缩应力。
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公开(公告)号：US20240304660A1
公开(公告)日：2024-09-12
申请号：US18666087
申请日：2024-05-16
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Korekiyo ITO
Abstract: A semiconductor device that includes a substrate; a first electrode layer on the substrate; a dielectric film on the first electrode layer, the dielectric film containing silicon oxide, and a ratio of three-membered ring structures to four-membered ring structures in the silicon oxide is 0.46 or less; a second electrode layer on the dielectric film; a protective layer covering the first electrode layer and the second electrode layer, and outer electrodes piercing the protective layer.
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