公开(公告)号：US20200266119A1

公开(公告)日：2020-08-20

申请号：US16497283

申请日：2018-03-28

Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Shiro HARA ,  Sommawan KHUMPUANG ,  Fumito IMURA

IPC: H01L23/12 ,  H01L21/677 ,  H01L21/56 ,  H01L23/544

Abstract: A method of manufacturing a semiconductor package and a semiconductor package in which positional alignment between a wafer and a substrate until the wafer is mounted and packaged on the substrate is achieved accurately. A wafer is mounted on a package substrate by using first alignment marks and D-cuts as benchmarks, and then a mold resin layer is formed on the wafer in a state in which the first alignment mark is exposed. A part of the mold resin layer is removed by using the D-cuts exposed from the mold resin layer as benchmarks, so that the first alignment marks can be visually recognized. A second alignment marks are formed on the mold resin layer by using the first alignment marks as benchmarks. A Cu redistribution layer to be conducted to a pad portion is formed on a mold resin layer by using the second alignment marks as benchmarks.

公开(公告)号：US20220341053A1

公开(公告)日：2022-10-27

申请号：US17718756

申请日：2022-04-12

Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Shiro HARA ,  Fumito IMURA ,  Sommawan KHUMPUANG ,  Yuuki ISHIDA ,  Toshihiro KIKUNO ,  Takafumi YOSHINAGA ,  Kayo KAMASAKI ,  Mitsuhiko FUKUYAMA ,  Tetuya MORIZONO

IPC: C25D17/08 ,  C25D17/00

Abstract: The plating machine 1 comprises a plurality of treatment units 14 and a conveying means 13 that conveys a wafer W to the plurality of treatment units 14, wherein the conveying means 13 includes an arm 31 that is provided, on one end side, with a plating tool 32 that holds the wafer W, and an arm rotation drive unit 33 that rotates the arm 31 around another end side of the arm 31, and the plurality of treatment units 14 is arranged at predetermined intervals on a rotation trajectory of the plating tool 32.

公开(公告)号：US20170352570A1

公开(公告)日：2017-12-07

申请号：US15529070

申请日：2015-11-24

Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Shiro HARA ,  Sommawan KHUMPUANG ,  Fumito IMURA ,  Michihiro INOUE ,  Arami SARUWATARI

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/6835 ,  H01L21/02 ,  H01L21/565 ,  H01L21/568 ,  H01L21/683 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68309 ,  H01L2221/68372 ,  H01L2223/54426 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2224/03 ,  H01L2924/00014

Abstract: An object of the present invention is to provide a circular support substrate that allows for positioning based solely on its outer periphery shape. As a means for solving the problems, a circular support substrate is provided that has at least three chords along its circumference, wherein the chords are provided at positions where they do not run linearly symmetrical to the straight line passing through the center axis of the circular support substrate.

公开(公告)号：US20170330741A1

公开(公告)日：2017-11-16

申请号：US15531237

申请日：2015-11-16

Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Michihiro INOUE ,  Shiro HARA ,  Fumito IMURA ,  Arami SARUWATARI ,  Sommawan KHUMPUANG

IPC: H01L21/02 ,  H01L21/677 ,  H01L21/673 ,  H01L23/544

CPC classification number: H01L21/02 ,  H01L21/6734 ,  H01L21/6773 ,  H01L21/67736 ,  H01L23/544 ,  H01L24/19 ,  H01L24/20 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A semiconductor manufacturing system has a series of steps, from manufacturing of a semiconductor on a wafer until packaging, that can be easily linked. A semiconductor chip manufacturing device manufactures a semiconductor chip, and a semiconductor packaging device packages the semiconductor chip by attaching the semiconductor chip to a package substrate which is larger than the wafer. The semiconductor chip manufacturing device includes a PLAD system for loading the wafer into and out of the semiconductor chip manufacturing device through a shuttle which is capable of housing the wafer. The semiconductor packaging device includes a PLAD system capable of loading the package substrate into and out of the semiconductor packaging device through a shuttle which is capable of housing the package substrate. The shuttles have container bodies of a same shape.

公开(公告)号：US20180025994A1

公开(公告)日：2018-01-25

申请号：US15529072

申请日：2015-11-24

Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Shiro HARA ,  Sommawan KHUMPUANG ,  Fumito IMURA ,  Michihiro INOUE ,  Arami SARUWATARI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L23/367

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/563 ,  H01L23/12 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/83805 ,  H01L2224/83851 ,  H01L2224/92244 ,  H01L2924/10155 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1461 ,  H01L2924/35121

Abstract: An object of the present invention is to provide a surface-mount type package for semiconductor chips which is resistant to failures caused by thermal stress. As a means for achieving the object, a method for manufacturing a surface-mount type package whose face parallel with the semiconductor chip surface has a circular cross-section, is provided, wherein such method is characterized in that it comprises at least the following steps in this order.A first step in which a semiconductor chip is bonded onto a circular support substrate.A second step in which the semiconductor chip is sealed with resin.A third step in which the resin covering the pads of the semiconductor chip is removed.A fourth step in which a rewiring layer is formed.A fifth step in which bumps are formed.