公开(公告)号：US6112307A

公开(公告)日：2000-08-29

申请号：US552460

申请日：1995-11-09

申请人： Jasmin Ajanovic ,  Dahmane Dahmani ,  Kenneth Chris Holland ,  Narendra Khandekar

发明人： Jasmin Ajanovic ,  Dahmane Dahmani ,  Kenneth Chris Holland ,  Narendra Khandekar

IPC分类号： G06F1/12 ,  H04L7/00 ,  H04L7/02 ,  G06F1/08

CPC分类号： G06F1/12 ,  H04L7/0012 ,  H04L7/02

摘要： A synchronizing circuit translates signals in a slow clock domain into a fast clock domain. The frequency of the slow clock is a submultiple of the fast clock frequency. A synchronizing pulse signal is developed at the frequency of the slow clock, but is phase synchronized to the fast clock. The synchronizing pulse signal is employed to gate the signal in the slow clock domain so that it is synchronized in the fast clock domain. In a system where the ratio between the fast clock frequency and slow clock frequency is determined by a frequency divisor signal, a snooping circuit is employed to capture the frequency divisor signal to achieve rapid synchronization between the clock domains.

摘要翻译： 同步电路将慢时钟域中的信号转换为快速时钟域。 慢时钟频率是快时钟频率的一个倍数。 在慢时钟的频率下产生同步脉冲信号，但是与快速时钟相位同步。 采用同步脉冲信号对慢时钟域中的信号进行门控，使其在快速时钟域中同步。 在快速时钟频率和慢时钟频率之间的比率由频率除数信号确定的系统中，采用窥探电路来捕获频率除数信号以实现时钟域之间的快速同步。

公开(公告)号：US5666556A

公开(公告)日：1997-09-09

申请号：US710572

申请日：1996-09-19

申请人： Narendra Khandekar ,  Jasmin Ajanovic

发明人： Narendra Khandekar ,  Jasmin Ajanovic

IPC分类号： G06F13/40 ,  G06F12/06

CPC分类号： G06F13/4027

摘要： A register address space is defined with a capacity large enough to accommodate substantial growth in the number of required registers. Unused register locations are reserved for future use. Access requests directed to reserved addresses are redirected to a physical register containing the same stored value that would be returned if a physical register were associated with the reserved address to which the access was originally directed. The physical register is separate from any central processing unit.

摘要翻译： 寄存器地址空间被定义为具有足够大的容量以容纳所需寄存器的数量的显着增长。 未使用的寄存器位置保留供将来使用。 指向保留地址的访问请求被重定向到物理寄存器，该物理寄存器包含与物理寄存器与访问最初指向的保留地址相关联时返回的相同存储值。 物理寄存器与任何中央处理单元分开。

公开(公告)号：US5519872A

公开(公告)日：1996-05-21

申请号：US175589

申请日：1993-12-30

申请人： Narendra Khandekar ,  Dahmane Dahmani ,  Jasmin Ajanovic

发明人： Narendra Khandekar ,  Dahmane Dahmani ,  Jasmin Ajanovic

IPC分类号： G06F13/42 ,  G06F13/364

CPC分类号： G06F13/4217

摘要： A latching mechanism captures an address transmitted on a multiplexed address/data bus and preserves it for the full bus cycle. A transparent latch with a multiplexed feedback path allows the address to be quickly captured and decoded. An additional multiplexer and latch cooperate with the first mentioned latch to keep the address stable for a sufficient time to allow latching by slower memory elements. Additional elements are provided to automatically increment the address for multiple data burst operation.

摘要翻译： 锁存机制捕获在复用的地址/数据总线上发送的地址，并将其保留在整个总线周期。 具有复用反馈路径的透明锁存器允许快速捕获和解码地址。 一个附加的多路复用器和锁存器与第一个提到的锁存器配合，以保持地址稳定足够的时间以允许较慢存储器元件的锁存。 提供附加元件以自动递增多个数据突发操作的地址。

公开(公告)号：US07000133B2

公开(公告)日：2006-02-14

申请号：US10104676

申请日：2002-03-22

申请人： James M. Dodd ,  Narendra Khandekar

发明人： James M. Dodd ,  Narendra Khandekar

IPC分类号： G06F1/26

CPC分类号： G06F1/3225

摘要： A method of controlling power states in a memory device includes determining if a power-down command is received. A first lower power state is entered if the power-down command is received and the memory device is in a first state. A second lower power state is entered if the power-down command is received and if the memory device is in a second state. The second lower power state is lower than the first lower power state. The memory device remains in a normal operation power state if the power-down command is not received.

摘要翻译： 控制存储器件中的电源状态的方法包括确定是否接收掉电命令。 如果接收到掉电命令并且存储器件处于第一状态，则输入第一低功率状态。 如果接收到掉电命令并且存储器件处于第二状态，则输入第二个较低功率状态。 第二低功率状态低于第一低功率状态。 如果没有接收到掉电命令，则存储器件保持在正常工作状态。

公开(公告)号：US5961649A

公开(公告)日：1999-10-05

申请号：US985391

申请日：1997-12-04

申请人： Narendra Khandekar ,  Ashish S. Gadagkar ,  Robert F. Kubick ,  Vincent E. VonBokern ,  Manish Muthal

发明人： Narendra Khandekar ,  Ashish S. Gadagkar ,  Robert F. Kubick ,  Vincent E. VonBokern ,  Manish Muthal

IPC分类号： G06F5/06 ,  G06F1/72

CPC分类号： G06F5/06

摘要： A method of transmitting a signal from a relatively fast clock domain to a relatively slow clock domain is described. The fast and slow clock domains operate according to respective fast and slow clock signals that are substantially synchronized and that have respective frequencies that are non-integer multiples. A first state of an input signal is latched at the commencement of a first period of the fast clock signal, the commencement of the first period of the fast clock signal being substantially coincident with the commencement of a first period of the slow clock signal. In response to the latching of the first state of the input signal, a first output signal is generated and held over the first period, and at least one further period, of the fast clock signal. The first output signal is then latched in the second time domain in response to the commencement of a second period of the slow clock signal, the second period being immediately subsequent to the first period of the slow clock signal.

摘要翻译： 描述了将信号从相对较快的时钟域发送到相对慢的时钟域的方法。 快速和慢速时钟域根据基本同步的相应的快速和慢速时钟信号进行操作，并且具有非整数倍的相应频率。 输入信号的第一状态在快时钟信号的第一周期的开始时被锁存，快速时钟信号的第一周期的开始基本上与慢时钟信号的第一周期的开始一致。 响应于输入信号的第一状态的锁存，在快速时钟信号的第一周期和至少另外一个周期内产生并保持第一输出信号。 响应于慢时钟信号的第二周期的开始，第一输出信号在第二时域被锁存，第二周期紧接在慢时钟信号的第一周期之后。

公开(公告)号：US06567904B1

公开(公告)日：2003-05-20

申请号：US08581378

申请日：1995-12-29

申请人： Narendra Khandekar ,  Aniruddha Kundu

发明人： Narendra Khandekar ,  Aniruddha Kundu

IPC分类号： G06F1200

CPC分类号： G11C7/1072 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/20 ,  G11C11/4072 ,  G11C2207/2254

摘要： A memory controller apparatus and method for automatically detecting whether a particular memory unit location is unpopulated or populated with synchronous dynamic random access memories (DRAMs), or asynchronous fast page (FP) DRAMs or extended data out (EDO) DRAMs are disclosed. Logic in the memory controller detects a memory device type by writing a first data item to the memory device using at least a minimum common asynchronous memory write protocol meeting the write timing requirements of all asynchronous memory device types. An attempt is then made to read the first data from the memory device using a first asynchronous memory read protocol. If the first data is read from the memory device, the memory device is identified as being an asynchronous memory. If the first data is not read from the device, the memory control logic writes a second data item to the memory device using a synchronous memory write protocol. An attempt is then made to read the second data from the memory device using a synchronous memory read protocol. If the second data is read, the memory device is identified as being a synchronous memory device. If the second data is not read, the memory unit is unpopulated. For one embodiment, the memory device type of each bank in a memory array is automatically stored in a configuration register such that a computer system is automatically configured to indicate memory device type.

摘要翻译： 公开了一种用于通过同步动态随机存取存储器（DRAM）或异步快速页（FP）DRAM或扩展数据输出（EDO）DRAM来自动检测特定存储器单元位置是否未填充或填充的存储器控​​制器装置和方法。 存储器控制器中的逻辑通过使用满足所有异步存储器设备类型的写定时要求的至少最小公共异步存储器写协议来将第一数据项写入存储器件来检测存储器件类型。 然后尝试使用第一异步存储器读协议从存储器件读取第一数据。 如果从存储器件读取第一数据，则存储器件被识别为异步存储器。 如果第一数据未从设备读取，则存储器控制逻辑使用同步存储器写协议将第二数据项写入存储器件。 然后尝试使用同步存储器读取协议从存储器件读取第二数据。 如果读取第二数据，则将存储器件识别为同步存储器件。 如果未读取第二数据，则存储器单元未被填充。对于一个实施例，存储器阵列中的每个存储体的存储器件类型被自动存储在配置寄存器中，使得计算机系统被自动配置为指示存储器件类型。

公开(公告)号：US06202112B1

公开(公告)日：2001-03-13

申请号：US09205351

申请日：1998-12-03

申请人： Ashish Gadagkar ,  Zohar Bogin ,  Narendra Khandekar ,  David D. Lent

发明人： Ashish Gadagkar ,  Zohar Bogin ,  Narendra Khandekar ,  David D. Lent

IPC分类号： G06F1342

CPC分类号： G06F13/4036

摘要： An embodiment of the invention is directed at a bridge having an outbound pipe for buffering transaction information and data being transported from various devices to a bus. The bridge has an arbiter for granting requests associated with these devices to access the outbound pipe for transferring the transaction information and data into the pipe. The bridge generates a reject signal in response to an initial request associated with an initial transaction from a first one of the devices if the outbound pipe is unavailable to accept further transaction information or data. The bridge has response control logic for generating a retry response for the initial transaction in response to the reject signal. The bridge is able to assert a stamp signal in response to the reject signal. The arbiter in response to the stamp being asserted waits, without granting any other lower priority requests to access the outbound pipe, until a subsequent transaction from the first device makes progress.

摘要翻译： 本发明的一个实施例涉及一种具有用于缓冲交易信息和从各种设备传输到总线的数据的出站管的桥。 桥接器具有用于授予与这些设备相关联的请求的仲裁器以访问出站管道，用于将事务信息和数据传送到管道中。 如果出站管道不可用于接受进一步的交易信息或数据，则桥接器响应于与来自第一设备的初始事务相关联的初始请求生成拒绝信号。 桥接器具有用于响应于拒绝信号而产生用于初始事务的重试响应的响应控制逻辑。 桥接器能够响应于拒绝信号来声明印记信号。 响应于该邮票被断言的仲裁者等待，而不允许任何其他较低优先级的请求访问出站管道，直到来自第一个设备的后续事务进行。

公开(公告)号：US6154825A

公开(公告)日：2000-11-28

申请号：US814733

申请日：1997-03-07

申请人： Robert N. Murdoch ,  Michael W. Williams ,  Kuljit Bains ,  Narendra Khandekar

发明人： Robert N. Murdoch ,  Michael W. Williams ,  Kuljit Bains ,  Narendra Khandekar

IPC分类号： G06F12/02 ,  G06F12/06 ,  G06F12/10

CPC分类号： G06F12/06 ,  G06F12/0215

摘要： A method and apparatus for accessing a memory resource, such as an array of DRAM modules, is described. The methodology commences with the receipt of a memory address during a memory access cycle. A row address is then generated by selecting predetermined bits of the memory address as the row address. Concurrently with the generation of the row address, a determination is made as to the configuration of a memory device within the memory resource and targeted by the memory address. Thereafter, a column address is generated by selecting bits of the memory address as the column address based on the configuration of the targeted memory device. The time required for the determination of the configuration of the targeted memory device is thus absorbed within the time expended generating the row address.

摘要翻译： 描述了用于访问诸如DRAM模块阵列之类的存储器资源的方法和装置。 该方法开始于在存储器访问周期期间接收到存储器地址。 然后通过选择存储器地址的预定位作为行地址来生成行地址。 与行地址的产生同时，确定存储器资源内的存储器设备的配置并且由存储器地址对准。 此后，基于目标存储器件的配置，通过选择存储器地址的位作为列地址来生成列地址。 因此，确定目标存储器件的配置所需的时间在生成行地址的时间内被吸收。

公开(公告)号：US5802603A

公开(公告)日：1998-09-01

申请号：US599056

申请日：1996-02-09

申请人： Kuljit Bains ,  Narendra Khandekar

发明人： Kuljit Bains ,  Narendra Khandekar

IPC分类号： G06F12/06 ,  G11C29/10 ,  G11C29/36 ,  G06F12/02

CPC分类号： G06F12/0684 ,  G11C29/10 ,  G11C29/36

摘要： A method and apparatus for detecting DRAM symmetry. A memory address including a row address and a column address bit is forced to a known value regardless of the host bit which would otherwise be mapped thereto. If the forced bit is in the column address it should be a bit which is not used by an asymmetric DRAM of the depth in the system to be tested, but would be used in a symmetric DRAM of the same depth. Conversely, if the forced bit is in the row address the bit should be used in the asymmetric case but not in the symmetric case. It is important that regardless of what bit in the memory address is forced, the forced bit should not be used by both cases at the depth tested. A first and second known value, are written respectively to two memory addresses which differ only in the value which would normally be mapped to this forced bit. The forced bit will cause an overwrite if the DRAM is of the type which uses the forced bit in its addressing. Thus, by reading the potentially overwritten address, symmetry is determined.

摘要翻译： 一种用于检测DRAM对称性的方法和装置。 包括行地址和列地址位的存储器地址被强制为已知值，而不管否则将映射到其的主机位。 如果强制位在列地址中，那么它应该是一个不被被测系统深度的非对称DRAM使用的位，但是将被用在相同深度的对称DRAM中。 相反，如果强制位在行地址中，那么该位应在非对称情况下使用，但不在对称情况下使用。 重要的是，无论内存地址中的哪一位被强制，强制位不应该在被测深度的情况下使用。 第一和第二已知值被分别写入两个存储器地址，这两个存储器地址仅在通常被映射到该强制位的值上不同。 如果DRAM是在其寻址中使用强制位的类型，则强制位将导致覆盖。 因此，通过读取可能覆盖的地址，确定对称性。

公开(公告)号：US20050071543A1

公开(公告)日：2005-03-31

申请号：US10674981

申请日：2003-09-29

申请人： Robert Ellis ,  Kuljit Bains ,  Chris Freeman ,  John Halbert ,  Narendra Khandekar ,  Michael Williams

发明人： Robert Ellis ,  Kuljit Bains ,  Chris Freeman ,  John Halbert ,  Narendra Khandekar ,  Michael Williams

IPC分类号： G06F13/16 ,  G11C5/00 ,  G11C11/406 ,  G06F12/00

CPC分类号： G11C11/406 ,  G06F13/1636 ,  G11C2211/4061

摘要： Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

摘要翻译： 在存储器总线上没有活动的情况下，独立于存储器控制器，在与存储器件相关联的存储器控​​制器的存储器总线的时间内，独立于存储器控制器，在存储器件中的行存储器单元上执行刷新操作的装置和方法。