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    Multiple Layer Resist Scheme Implementing Etch Recipe Particular to Each Layer
    1.
    发明申请
    Multiple Layer Resist Scheme Implementing Etch Recipe Particular to Each Layer 有权
    多层抗扰性方案实现每层专用的蚀刻配方

    公开(公告)号：US20060094230A1

    公开(公告)日：2006-05-04

    申请号：US10904323

    申请日：2004-11-04

    Applicant: Nicholas Fuller ,  Timothy Dalton ,  Raymond Joy ,  Yi-hsiung Lin ,  Chun Low

    Inventor： Nicholas Fuller ,  Timothy Dalton ,  Raymond Joy ,  Yi-hsiung Lin ,  Chun Low

    IPC: H01L21/4763

    CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/31138 ,  H01L21/31144

    Abstract: Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.

    Abstract translation: 公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸（CD）的方法和实现的抗蚀剂方案。 该方法包括形成多层抗蚀剂方案，该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层，平坦化层上的第二类型材料的第二电介质层，以及在电介质上的第三类型材料的第三光致抗蚀剂层 层。 有机材料和无机材料之间的材料类型是交替的。 第三层被图案化为金属线和/或经由CD。 然后使用对每一个被暴露的第一光致抗蚀剂层，第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。 提供准确的CD形成和足够的抗蚀剂预算。

    Method of forming an interconnect structure
    2.
    发明申请
    Method of forming an interconnect structure 失效
    形成互连结构的方法

    公开(公告)号：US20070148966A1

    公开(公告)日：2007-06-28

    申请号：US11315923

    申请日：2005-12-22

    Applicant: Heidi Baks ,  Shyng-Tsong Chen ,  Timothy Dalton ,  Nicholas Fuller ,  Kaushik Kumar

    Inventor： Heidi Baks ,  Shyng-Tsong Chen ,  Timothy Dalton ,  Nicholas Fuller ,  Kaushik Kumar

    IPC: H01L21/4763

    CPC classification number: H01L21/76802 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76811

    Abstract: A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and plasma photoresist removal processes and performing one or more additional plasma etch processes that do not include oxygen containing species to etch the openings to depths required for forming the damascene interconnect structures and to remove any organo-silicate material damaged by the combination of plasma etch and plasma photoresist removal processes.

    Abstract translation: 在有机硅酸盐玻璃层中形成镶嵌互连结构而不会损坏有机硅酸盐玻璃材料的方法。 该方法包括在有机硅酸盐玻璃层上形成硬掩模层堆叠，使用等离子体蚀刻和等离子体光致抗蚀剂去除方法的组合在硬掩模和有机硅酸盐玻璃层中限定开口，并执行一个或多个额外的等离子体蚀刻工艺 不包括含氧物质，以将开口蚀刻到形成镶嵌互连结构所需的深度，并除去由等离子体蚀刻和等离子体光致抗蚀剂去除工艺的组合损坏的任何有机硅酸盐材料。

    DE-FLUORINATION AFTER VIA ETCH TO PRESERVE PASSIVATION
    5.
    发明申请
    DE-FLUORINATION AFTER VIA ETCH TO PRESERVE PASSIVATION 失效
    经过灭火后进行灭火

    公开(公告)号：US20060099785A1

    公开(公告)日：2006-05-11

    申请号：US10904432

    申请日：2004-11-10

    Applicant: Nicholas Fuller ,  Timothy Dalton

    Inventor： Nicholas Fuller ,  Timothy Dalton

    IPC: H01L21/44

    CPC classification number: H01L21/76807 ,  H01L21/02063

    Abstract: Novel interconnect structures possessing a dense OSG material for 90 nm and beyond BEOL technologies in which a low power density oxygen-based de-fluorination plasma process is utilized to increase NBLoK selectivity are presented. These BEOL interconnect structures are capable of delivering enhanced reliability and performance due to the reduced risk of Cu exposure and hence electromigration and stress migration related failures. The oxygen based de-fluorination process is such that the plasma conditions employed {low power density ( 100 mT); negligible ion current to wafer surface (applied source frequency only)} facilitate a physical expulsion of residual fluorine present on the chamber walls, wafer surface, and within the via structure; thus, minimizing the extent of NBLoK etching that can occur subsequent to removing polymeric byproducts of via etching.

    Abstract translation: 提出了具有用于90nm以上的致密OSG材料的新型互连结构，并且提出了使用低功率密度氧基脱氟等离子体工艺来提高NBLoK选择性的BEOL技术。 这些BEOL互连结构能够提供增强的可靠性和性能，因为Cu暴露的风险降低，因此电迁移和压力迁移相关故障。 基于氧的脱氟方法是使用等离子体条件{低功率密度（<0.3WCM <-22）; 相对高压（> 100 mT）; 可忽略离子电流到晶片表面（仅施加源频率）}有助于物理排出存在于室壁，晶片表面和通孔结构内的残留氟; 从而最小化在去除通孔蚀刻的聚合物副产物之后可能发生的NBLoK蚀刻的程度。

    Photoresist ash process with reduced inter-level dielectric ( ILD) damage
    6.
    发明申请
    Photoresist ash process with reduced inter-level dielectric ( ILD) damage 审中-公开
    具有降低的层间电介质（ILD）损伤的光刻胶灰工艺

    公开(公告)号：US20050077629A1

    公开(公告)日：2005-04-14

    申请号：US10685012

    申请日：2003-10-14

    Applicant: Timothy Dalton ,  Nicholas Fuller ,  Kaushik Kumar

    Inventor： Timothy Dalton ,  Nicholas Fuller ,  Kaushik Kumar

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/48

    CPC classification number: H01L21/76802 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Novel interconnect structures possessing an organosilicate dielectric material with unaltered physical and chemical properties post exposure to a specific resist ash chemistry for use in semiconductor devices are provided herein. The novel interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the use of a chemically and physically “friendly” resist ash process. An in situ inert gas/H2 process achieves minimal chemical and physical reactivity with the organosilicate sidewalls during ashing owing to its inherent make up.

    Abstract translation: 本文提供了具有在暴露于用于半导体器件的特定抗蚀剂灰化学物质之后具有未改变的物理和化学性质的有机硅酸盐介电材料的新型互连结构。 由于使用了化学和物理上“友好”的抗蚀灰工艺，新颖的互连结构能够提供改进的器件性能，功能和可靠性。 原位惰性气体/ H2过程由于其固有的组成而在灰化过程中与有机硅酸盐侧壁产生最小的化学和物理反应性。

    HIGH ION ENERGY AND REATIVE SPECIES PARTIAL PRESSURE PLASMA ASH PROCESS
    10.
    发明申请
    HIGH ION ENERGY AND REATIVE SPECIES PARTIAL PRESSURE PLASMA ASH PROCESS 有权
    高离子能量和重要物质部分压力等离子体ASH过程

    公开(公告)号：US20060105576A1

    公开(公告)日：2006-05-18

    申请号：US10904608

    申请日：2004-11-18

    Applicant: Nicholas Fuller ,  Timothy Dalton

    Inventor： Nicholas Fuller ,  Timothy Dalton

    IPC: H01L21/00 ,  H01L21/84 ,  H01L21/302 ,  H01L21/461

    CPC classification number: H01L21/76802 ,  G03F7/427 ,  H01L21/31138

    Abstract: A high ion energy and high pressure O2/CO-based plasma for ashing field photoresist material subsequent to via-level damascene processing. The optimized plasma ashing process is performed at greater than approximately 300 mT pressure and ion energy greater than approximately 500 W conditions with an oxygen partial pressure of greater than approximately 85%. The rapid ash rate of the high pressure/high ion energy process and minimal dissociation conditions (no “source” power is applied) allow minimal interaction between the interlevel dielectric and ash chemistry to achieve minimal overall sidewall modification of less than approximately 5 nm.

    Abstract translation: 用于经过层级镶嵌处理之后灰化场致光材料的高离子能量和高压O 2 2 / CO基等离子体。 优化的等离子体灰化过程在大于约300mT的压力下进行，离子能量大于约500W条件，氧分压大于约85％。 高压/高离子能量过程的快速灰分速率和最小解离条件（不施加“源”功率）允许层间电介质和灰分化学之间的最小相互作用，以实现小于约5nm的最小总体侧壁修饰。

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