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公开(公告)号：US20180226509A1
公开(公告)日：2018-08-09
申请号：US15747925
申请日：2015-07-31
申请人： Elijah V. Karpov , Prashant Majhi , Roza Kotlyar , Niloy Mukherjee , Charles C. Kuo , Uday Shah , Ravi Pillarisetty , Robert S. Chau
发明人： Elijah V. Karpov , Prashant Majhi , Roza Kotlyar , Niloy Mukherjee , Charles C. Kuo , Uday Shah , Ravi Pillarisetty , Robert S. Chau
IPC分类号： H01L29/786 , H01L27/07 , H01L27/12 , H01L29/49 , H01L29/02
CPC分类号： H01L29/7869 , H01L27/0705 , H01L27/1225 , H01L27/2436 , H01L29/02 , H01L29/4908 , H01L29/78603 , H01L29/78642 , H01L45/04 , H01L45/1206 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.
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公开(公告)号：US10516109B2
公开(公告)日：2019-12-24
申请号：US15529907
申请日：2014-12-24
申请人： Niloy Mukherjee , Ravi Pillarisetty , Prashant Majhi , Uday Shah , Ryan E Arch , Markus Kuhn , Justin S. Brockman , Huiying Liu , Elijah V Karpov , Kaan Oguz , Brian S. Doyle , Robert S. Chau
发明人： Niloy Mukherjee , Ravi Pillarisetty , Prashant Majhi , Uday Shah , Ryan E Arch , Markus Kuhn , Justin S. Brockman , Huiying Liu , Elijah V Karpov , Kaan Oguz , Brian S. Doyle , Robert S. Chau
IPC分类号： H01L45/00
摘要： Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.
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公开(公告)号：US10355205B2
公开(公告)日：2019-07-16
申请号：US15528674
申请日：2014-12-18
申请人： Prashant Majhi , Ravi Pillarisetty , Niloy Mukherjee , Uday Shah , Elijah V. Karpov , Brian S. Doyle , Robert S. Chau
发明人： Prashant Majhi , Ravi Pillarisetty , Niloy Mukherjee , Uday Shah , Elijah V. Karpov , Brian S. Doyle , Robert S. Chau
摘要： Resistive memory cells are described. In some embodiments, the resistive memory cells include a switching layer having an inner region in which one or more filaments is formed. In some instances, the filaments is/are formed only within the inner region of the switching layer. Methods of making such resistive memory cells and devices including such cells are also described.
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公开(公告)号：US20150091067A1
公开(公告)日：2015-04-02
申请号：US14040574
申请日：2013-09-27
申请人： Ravi Pillarisetty , Brian S. Doyle , Elijah V. Karpov , David L. Kencke , Uday Shah , Charles C. Kuo , Robert S. Chau
发明人： Ravi Pillarisetty , Brian S. Doyle , Elijah V. Karpov , David L. Kencke , Uday Shah , Charles C. Kuo , Robert S. Chau
CPC分类号： H01L27/2436 , H01L29/66477 , H01L29/66568 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L2029/7858
摘要： An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.
摘要翻译： 在晶体管结构上沉积绝缘层。 晶体管结构包括位于衬底上的器件层上的栅电极。 晶体管结构包括在栅电极的相对侧的器件层上的第一接触区域和第二接触区域。 在第一接触区域上的第一绝缘层中形成沟槽。 具有S形IV特性的金属 - 绝缘体相变材料层沉积在源极侧上方的金属化层的沟槽或通路中。
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公开(公告)号：US20140061589A1
公开(公告)日：2014-03-06
申请号：US14057204
申请日：2013-10-18
申请人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号： H01L29/775
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。
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公开(公告)号：US20110156005A1
公开(公告)日：2011-06-30
申请号：US12655468
申请日：2009-12-30
申请人： Ravi Pillarisetty , Been-Yih Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人： Ravi Pillarisetty , Been-Yih Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号： H01L29/772
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。
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公开(公告)号：US08592803B2
公开(公告)日：2013-11-26
申请号：US13442098
申请日：2012-04-09
申请人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号： H01L29/06 , H01L29/778
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
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公开(公告)号：US20120193609A1
公开(公告)日：2012-08-02
申请号：US13442098
申请日：2012-04-09
申请人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号： H01L29/66
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。
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公开(公告)号：US08193523B2
公开(公告)日：2012-06-05
申请号：US12655468
申请日：2009-12-30
申请人： Ravi Pillarisetty , Been-Yih Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人： Ravi Pillarisetty , Been-Yih Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅介电材料允许使用高k值栅极电介质。
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公开(公告)号：US08987091B2
公开(公告)日：2015-03-24
申请号：US13976840
申请日：2011-12-23
申请人： Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
发明人： Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336 , H01L31/00 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/778 , H01L29/40 , H01L29/20
CPC分类号： H01L29/7787 , H01L21/02241 , H01L21/02252 , H01L21/02255 , H01L21/02258 , H01L21/02458 , H01L21/0254 , H01L21/268 , H01L21/30604 , H01L21/30612 , H01L21/31111 , H01L29/2003 , H01L29/205 , H01L29/365 , H01L29/401 , H01L29/4236 , H01L29/512 , H01L29/518 , H01L29/66462
摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
摘要翻译： 具有凹入栅极的III-N晶体管。 外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和III-N沟道层之间的III-N蚀刻停止层。 蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。 栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。 蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化物的凹陷栅III-N MOS-HEMT。 可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。
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