摘要:
A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing over the charge trapping dielectric flash memory cell at least one UV-protective layer; forming at least one layer over the at least one UV-protective layer; and etching the at least one layer to form an opening therein with an etchant species selective to stop on a layer below the at least one UV-protective layer, wherein the UV-protective layer comprises a substantially UV-opaque material.
摘要:
The invention includes an apparatus and a method of manufacturing such apparatus using a damascene process. The method includes the step of patterning a layer disposed over a substrate to include a line and space pattern. The line and space pattern in the layer includes at least one space comprising a width dimension of a feature to be formed. The feature may be, e.g., a wordline(s)/gate electrode(s). Additionally, the sidewalls of the feature, e.g., the wordline(s)/gate electrode(s) include relatively smooth surfaces.
摘要:
A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing and planarizing an interlevel dielectric layer over the charge trapping dielectric flash memory cell and depositing over the planarized interlevel dielectric layer at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material.
摘要:
A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device; and during processing steps subsequent to formation of the charge trapping dielectric charge storage layer, protecting the charge trapping dielectric flash memory cell from exposure to a level of UV radiation sufficient to deposit a non-erasable charge in the charge trapping dielectric flash memory cell. In one embodiment, the step of protecting is carried out by selecting processes in BEOL fabrication which do not include use, generation or exposure of the semiconductor device to a level of UV radiation sufficient to deposit the non-erasable charge.
摘要:
A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls. The oxide is removed to expose the substrate between insulating spacers in the bit line regions and a conductor is fabricated thereon to enhance conductivity of each bit line.
摘要:
In one embodiment, the present invention relates to a method for pre-treating and etching a dielectric layer in a semiconductor device comprising the steps of: (A) pre-treating one or more exposed portions of a dielectric layer with a plasma in a plasma etching tool to increase removal rate of the one or more exposed portions upon etching; and (B) removing the one or more exposed portions of the dielectric layer in the same plasma etching tool of step (A) via plasma etching.
摘要:
The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.
摘要:
A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate, a bottom dielectric, a charge storing layer, and a top dielectric in a stacked gate configuration. Silicided buried bitlines, which function as a source and a drain, are formed within the substrate. The silicided bitlines have a reduced resistance, which greatly reduces the number of bitline contacts necessary in an array of memory devices.
摘要:
A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.
摘要:
The invention is an apparatus and a method of manufacturing a structure. The method includes the step of patterning a layer to include a line and space pattern. A space of the line and space pattern in a first region includes a first critical dimension less than achievable at a resolution limit of lithography. A line of the line and space pattern in a second region includes a second critical dimension achievable at a resolution limit of lithography. A sidewall spacer is formed on a line from a masking layer used in the formation of the structure. The method uses one critical masking step and two non-critical masking steps.