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265 条记录 (耗时 0.032 秒)

    Method for semiconductor wafer planarization by CMP stop layer formation
    4.
    发明授权
    Method for semiconductor wafer planarization by CMP stop layer formation 失效
    通过CMP停止层形成的半导体晶片平面化方法

    公开(公告)号：US06770523B1

    公开(公告)日：2004-08-03

    申请号：US10190397

    申请日：2002-07-02

    申请人： Kashmir S. Sahota ,  Jeffrey P. Erhardt ,  Arvind Halliyal ,  Minh Van Ngo ,  Krishnashree Achuthan

    发明人： Kashmir S. Sahota ,  Jeffrey P. Erhardt ,  Arvind Halliyal ,  Minh Van Ngo ,  Krishnashree Achuthan

    IPC分类号： H01L218238

    CPC分类号： H01L21/76229 ,  H01L21/31053

    摘要： A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.

    摘要翻译： 提供了具有半导体晶片的集成电路的制造方法。 化学机械抛光停止层沉积在半导体晶片上，并且在化学机械抛光停止层上处理第一光致抗蚀剂层。 化学机械抛光停止层和半导体晶片被图案化以形成浅沟槽，浅沟槽隔离材料沉积在化学机械抛光停止层和浅沟槽中。 在浅沟槽隔离材料上处理第二光致抗蚀剂层，留下未覆盖的浅沟槽。 然后将未覆盖的浅沟槽处理成为化学机械抛光停止区域。 然后将浅沟槽隔离材料进行化学机械抛光以与化学 - 机械停止层和化学 - 机械抛光停止处理区共面。

    Treatment of dielectric material to enhance etch rate
    5.
    发明授权
    Treatment of dielectric material to enhance etch rate 有权
    处理电介质材料以提高蚀刻速率

    公开(公告)号：US06905971B1

    公开(公告)日：2005-06-14

    申请号：US10331938

    申请日：2002-12-30

    申请人： Cyrus Tabery ,  Chih-Yuh Yang ,  William G. En ,  Joong S. Jeon ,  Minh Van Ngo ,  Ming-Ren Lin

    发明人： Cyrus Tabery ,  Chih-Yuh Yang ,  William G. En ,  Joong S. Jeon ,  Minh Van Ngo ,  Ming-Ren Lin

    IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/461

    CPC分类号： H01L21/31116 ,  H01L21/31122

    摘要： In one embodiment, the present invention relates to a method for pre-treating and etching a dielectric layer in a semiconductor device comprising the steps of: (A) pre-treating one or more exposed portions of a dielectric layer with a plasma in a plasma etching tool to increase removal rate of the one or more exposed portions upon etching; and (B) removing the one or more exposed portions of the dielectric layer in the same plasma etching tool of step (A) via plasma etching.

    摘要翻译： 在一个实施例中，本发明涉及一种用于在半导体器件中预处理和蚀刻电介质层的方法，包括以下步骤：（A）用等离子体中的等离子体预处理介电层的一个或多个暴露部分 蚀刻工具，以在蚀刻时增加一个或多个暴露部分的去除速率; 和（B）通过等离子体蚀刻在步骤（A）的相同等离子体蚀刻工具中去除介电层的一个或多个暴露部分。

    Silicon containing material for patterning polymeric memory element
    7.
    发明授权
    Silicon containing material for patterning polymeric memory element 有权
    含硅材料用于图案化聚合物记忆元件

    公开(公告)号：US06803267B1

    公开(公告)日：2004-10-12

    申请号：US10614484

    申请日：2003-07-07

    申请人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

    发明人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

    IPC分类号： H01L21336

    CPC分类号： H01L27/28 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0018

    摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.

    摘要翻译： 本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料 上电极通过有机半导体材料和被动材料到下电极。 有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。 此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。 分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。

    Multi-cell organic memory element and methods of operating and fabricating
    9.
    发明授权
    Multi-cell organic memory element and methods of operating and fabricating 有权
    多单元有机存储元件及其操作和制造方法

    公开(公告)号：US06900488B1

    公开(公告)日：2005-05-31

    申请号：US10284946

    申请日：2002-10-31

    申请人： Sergey D. Lopatin ,  Mark S. Chang ,  Minh Van Ngo ,  Patrick K. Cheung

    发明人： Sergey D. Lopatin ,  Mark S. Chang ,  Minh Van Ngo ,  Patrick K. Cheung

    IPC分类号： H01L27/28 ,  H01L51/00 ,  H01L51/30 ,  H01L51/40 ,  H01L29/76

    CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0021 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0038 ,  H01L51/0041 ,  H01L51/0077 ,  H01L51/0078

    摘要： The present invention provides a multi-cell organic memory device that can operate as a non-volatile memory device having a plurality of multi-cell structures constructed within the memory device. A lower electrode can be formed, wherein one or more passive layers are formed on top of the lower electrode. An Inter Layer Dielectric (ILD) is formed above the passive layers and lower electrode, whereby a via or other type relief is created within the ILD and an organic semiconductor material is then utilized to partially fill the via above the passive layer. The portions of the via that are not filled with organic material are filled with dielectric material, thus forming a multi-dimensional memory structure above the passive layer or layers and the lower electrode. One or more top electrodes are then added above the memory structure, whereby distinctive memory cells are created within the organic portions of the memory structure and activated (e.g., read/write) between the top electrodes and bottom electrode, respectively. In this manner, multiple storage cells can be formed within a singular organic structure thereby increasing memory device density and storage.

    摘要翻译： 本发明提供一种多小区有机存储装置，其可以作为具有构造在存储装置内的多个多小区结构的非易失性存储装置来操作。 可以形成下电极，其中在下电极的顶部上形成一个或多个钝化层。 在无源层和下电极之上形成层间电介质（ILD），由此在ILD内产生通孔或其它类型的浮雕，然后利用有机半导体材料部分地填充钝化层以上的通孔。 通孔中没有填充有机材料的部分用电介质材料填充，从而在钝化层或下层电极之上形成多维存储结构。 然后在存储器结构上方添加一个或多个顶部电极，由此在存储器结构的有机部分内分别创建独特的存储单元，并分别在顶部电极和底部电极之间激活（例如，读取/写入）。 以这种方式，可以在单个有机结构内形成多个存储单元，从而增加存储器件密度和存储。