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公开(公告)号:US09592664B2
公开(公告)日:2017-03-14
申请号:US14343133
申请日:2011-09-27
申请人: Ning Ge , Paul I. Mikulan , Bee Ling Peh
发明人: Ning Ge , Paul I. Mikulan , Bee Ling Peh
IPC分类号: G11C16/04 , B41J29/38 , B41J2/045 , H01L29/788 , H01L27/115 , G11C11/56
CPC分类号: G06F3/061 , B41J2/04541 , B41J2/04581 , B41J2/04586 , G06F3/0655 , G06F3/0688 , G11C11/5621 , G11C16/0433 , G11C16/0458 , H01L27/11521 , H01L29/7881 , H01L29/7887
摘要: An integrated circuit including a first EPROM, a second EPROM, and a circuit. The first EPROM is configured to provide a first state and a second state. The second EPROM is configured to provide a third state and a fourth state. The circuit is configured to select the first EPROM and the second EPROM individually and in parallel with each other.
摘要翻译: 一种包括第一EPROM,第二EPROM和电路的集成电路。 第一EPROM被配置为提供第一状态和第二状态。 第二EPROM被配置为提供第三状态和第四状态。 电路被配置为分别并且彼此并行地选择第一EPROM和第二EPROM。
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公开(公告)号:US20140218436A1
公开(公告)日:2014-08-07
申请号:US14343133
申请日:2011-09-27
申请人: Ning Ge , Paul I. Mikulan , Bee Ling Peh
发明人: Ning Ge , Paul I. Mikulan , Bee Ling Peh
CPC分类号: G06F3/061 , B41J2/04541 , B41J2/04581 , B41J2/04586 , G06F3/0655 , G06F3/0688 , G11C11/5621 , G11C16/0433 , G11C16/0458 , H01L27/11521 , H01L29/7881 , H01L29/7887
摘要: An integrated circuit including a first EPROM, a second EPROM, and a circuit. The first EPROM is configured to provide a first state and a second state. The second EPROM is configured to provide a third state and a fourth state. The circuit is configured to select the first EPROM and the second EPROM individually and in parallel with each other.
摘要翻译: 一种包括第一EPROM,第二EPROM和电路的集成电路。 第一EPROM被配置为提供第一状态和第二状态。 第二EPROM被配置为提供第三状态和第四状态。 电路被配置为分别并且彼此并行地选择第一EPROM和第二EPROM。
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公开(公告)号:US06740536B2
公开(公告)日:2004-05-25
申请号:US10055161
申请日:2001-10-26
IPC分类号: H01L2100
CPC分类号: B41J2/14072 , B41J2/14129 , B41J2202/13
摘要: Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.
摘要翻译: 提供了集成电路及其制造方法。 特别地,提供了具有屏蔽元件的集成电路。
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公开(公告)号:US08444255B2
公开(公告)日:2013-05-21
申请号:US13110615
申请日:2011-05-18
申请人: Chris Bakker , Lawrence H. White , Bjorn Warloe , Reynaldo V. Villavelez , Paul I. Mikulan , Kenneth Stewart , Michael Allen Godwin , Teck-Khim Neo , Joseph M. Torgerson , Lonnie Byers
发明人: Chris Bakker , Lawrence H. White , Bjorn Warloe , Reynaldo V. Villavelez , Paul I. Mikulan , Kenneth Stewart , Michael Allen Godwin , Teck-Khim Neo , Joseph M. Torgerson , Lonnie Byers
IPC分类号: B41J2/05
CPC分类号: B41J2/14129 , Y10T29/49401
摘要: A thermal inkjet printhead may include a substrate and a resistive layer. A thermal resistor may be formed in the resistive layer. A first metal layer may be between the substrate and a resistive layer having a thickness to form a power bus. A dielectric layer may be between the first metal layer and the resistive layer.
摘要翻译: 热喷墨打印头可以包括基底和电阻层。 可以在电阻层中形成热电阻。 第一金属层可以在衬底和具有形成电源母线的厚度的电阻层之间。 电介质层可以在第一金属层和电阻层之间。
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公开(公告)号:US09524780B2
公开(公告)日:2016-12-20
申请号:US14000620
申请日:2011-03-15
IPC分类号: G11C5/06 , G11C16/10 , H01L21/28 , H01L27/115 , H01L29/788 , H01L29/423 , H01L29/66 , H01L29/06
CPC分类号: H01L27/11524 , B41J2/04541 , B41J2/04586 , G11C16/10 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/1033 , H01L29/42324 , H01L29/66825 , H01L29/788 , H01L29/7884
摘要: A memory cell including a drain, a channel, and a floating gate. The channel surrounds the drain and includes a first rounded closed curve structure around the drain. The floating gate is situated over the channel and includes a second rounded closed curve structure over the channel.
摘要翻译: 存储单元,包括漏极,沟道和浮置栅极。 通道围绕排水管并且包括围绕排水管的第一圆形闭合曲线结构。 浮动栅极位于通道上方,并且在通道上包括第二圆形闭合曲线结构。
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公开(公告)号:US08476742B2
公开(公告)日:2013-07-02
申请号:US12812776
申请日:2008-02-28
申请人: Gregory N. Burton , Paul I. Mikulan
发明人: Gregory N. Burton , Paul I. Mikulan
IPC分类号: H01L23/485
CPC分类号: B41J2/14129 , B41J2002/14387 , B41J2202/18 , H01L21/76804 , H01L21/76805 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要: Edges of a first conductive layer (104) and a silicate glass layer (106) extend adjacent one another along a via (164) extending to a semiconductor substrate (41). An electrical conductor (112/114) extends through the via (164) into contact with the semiconductor substrate (41).
摘要翻译: 第一导电层(104)和硅酸盐玻璃层(106)的边缘沿着延伸到半导体衬底(41)的通孔(164)彼此相邻延伸。 电导体(112/114)延伸穿过通孔(164)与半导体衬底(41)接触。
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公开(公告)号:US07488611B2
公开(公告)日:2009-02-10
申请号:US11294822
申请日:2005-12-06
IPC分类号: H01L21/00
CPC分类号: B41J2/14129 , B41J2/14072 , B41J2/1603 , B41J2/1629 , B41J2/1631
摘要: Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.
摘要翻译: 提供了集成电路及其制造方法。 特别地,提供了具有屏蔽元件的集成电路。
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公开(公告)号:US20130329498A1
公开(公告)日:2013-12-12
申请号:US14000620
申请日:2011-03-15
IPC分类号: G11C16/10 , H01L29/788
CPC分类号: H01L27/11524 , B41J2/04541 , B41J2/04586 , G11C16/10 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/1033 , H01L29/42324 , H01L29/66825 , H01L29/788 , H01L29/7884
摘要: A memory cell including a drain, a channel, and a floating gate. The channel surrounds the drain and includes a first rounded closed curve structure around the drain. The floating gate is situated over the channel and includes a second rounded closed curve structure over the channel.
摘要翻译: 存储单元,包括漏极,沟道和浮置栅极。 通道围绕排水管并且包括围绕排水管的第一圆形闭合曲线结构。 浮动栅极位于通道上方,并且在通道上包括第二圆形闭合曲线结构。
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公开(公告)号:US20100320608A1
公开(公告)日:2010-12-23
申请号:US12812776
申请日:2008-02-28
申请人: Gregory N. Burton , Paul I. Mikulan
发明人: Gregory N. Burton , Paul I. Mikulan
IPC分类号: H01L23/48 , H01L21/768
CPC分类号: B41J2/14129 , B41J2002/14387 , B41J2202/18 , H01L21/76804 , H01L21/76805 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要: Edges of a first conductive layer (104) and a silicate glass layer (106) extend adjacent one another along a via (164) extending to a semiconductor substrate (41). An electrical conductor (112/114) extends through the via (164) into contact with the semiconductor substrate (41).
摘要翻译: 第一导电层(104)和硅酸盐玻璃层(106)的边缘沿着延伸到半导体衬底(41)的通孔(164)彼此相邻延伸。 电导体(112/114)延伸穿过通孔(164)与半导体衬底(41)接触。
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10.
公开(公告)号:US09536112B2
公开(公告)日:2017-01-03
申请号:US13495292
申请日:2012-06-13
CPC分类号: G06F21/73 , G06F21/44 , H04L9/3278
摘要: In an embodiment, to deter or delay counterfeiting/cloning of a replacement component of a host device, the replacement component is provided with a code value. The code value is generated from a value of at least one physical parameter of the replacement component and is stored on the replacement component. The host device determines whether the replacement component is authentic if the stored code value matches a reference code value.
摘要翻译: 在一个实施例中,为了阻止或延迟伪装/克隆主机设备的替换部件,替换部件被提供有代码值。 代码值是从替换组件的至少一个物理参数的值生成的,并存储在替换组件上。 如果存储的代码值与参考代码值匹配,则主机设备确定替换组件是否可信。
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