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    Pipeline-operating type memory system capable of reading data from a memory array having data width larger than the output data width
    1.
    发明授权
    Pipeline-operating type memory system capable of reading data from a memory array having data width larger than the output data width 失效
    能够从具有大于输出数据宽度的数据宽度的存储器阵列中读取数据的管道操作型存储器系统

    公开(公告)号：US5619455A

    公开(公告)日：1997-04-08

    申请号：US35651

    申请日：1993-03-23

    申请人： Noboru Akiyama ,  Yuji Yokoyama ,  Tatsuyuki Ohta ,  Kunihiko Suzuki ,  Yutaka Kobayashi

    发明人： Noboru Akiyama ,  Yuji Yokoyama ,  Tatsuyuki Ohta ,  Kunihiko Suzuki ,  Yutaka Kobayashi

    IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/34 ,  G11C7/00

    CPC分类号： G11C7/1039

    摘要： A pipeline-operating type memory system is arranged to have a first input unit for receiving a selector address signal for selecting data; a second input unit for receiving at least an address strobe signal, an X address signal and a Y address signal for selecting data; a first unit for receiving the X address signal and the Y address signal, latching these signals utilizing a first clock signal, and continuously outputting at least either of the X and the Y address signals until these address signals are unlatched; and a second unit for latching a selector address data signal output from the first input unit utilizing the first clock signal, and continuously and selectively outputting at least either of the address signal until the signal is unlatched. The memory system operates to transfer data in a manner to suit the pipeline operating cycle at a normal operating mode and at a fast page mode.

    摘要翻译： 流水线操作型存储器系统被布置成具有用于接收用于选择数据的选择器地址信号的第一输入单元; 第二输入单元，用于至少接收地址选通信号，X地址信号和Y地址信号，用于选择数据; 用于接收X地址信号和Y地址信号的第一单元，利用第一时钟信号锁存这些信号，并且连续地输出X和Y地址信号中的至少一个，直到这些地址信号被解锁为止; 以及第二单元，用于使用所述第一时钟信号来锁存从所述第一输入单元输出的选择器地址数据信号，并且连续且选择性地输出所述地址信号中的至少一个，直到所述信号被解锁为止。 存储器系统操作以在正常操作模式和快速页模式下以适合流水线操作周期的方式传送数据。

    Pipeline-operating type memory system capable of reading data from a memory array having data width larger than the output data width
    2.
    发明授权
    Pipeline-operating type memory system capable of reading data from a memory array having data width larger than the output data width 失效
    能够从具有大于输出数据宽度的数据宽度的存储器阵列中读取数据的管道操作型存储器系统

    公开(公告)号：US5602782A

    公开(公告)日：1997-02-11

    申请号：US467276

    申请日：1995-06-06

    申请人： Noboru Akiyama ,  Yuji Yokoyama ,  Tatsuyuki Ohta ,  Kunihiko Suzuki ,  Yutaka Kobayashi

    发明人： Noboru Akiyama ,  Yuji Yokoyama ,  Tatsuyuki Ohta ,  Kunihiko Suzuki ,  Yutaka Kobayashi

    IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/34 ,  G11C7/00

    CPC分类号： G11C7/1039

    摘要： A pipeline-operating type memory system is arranged to have a first input unit for receiving a selector address signal for selecting data, a second input unit for receiving at least an address strobe signal, an X address signal and a Y address signal for selecting data; a first unit for receiving the X address signal and the Y address signal, latching these signals utilizing a first clock signal, and continuously outputting at least either of the X and the Y address signals until these address signals are unlatched; and a second unit for latching a selector address data signal output from the first input unit utilizing the first clock signal, and continuously and selectively outputting at least either of the address signal until the signal is unlatched. The memory system operates to transfer data in a manner to suit the pipeline operating cycle at a normal operating mode and at a fast page mode.

    摘要翻译： 流水线操作型存储器系统被布置成具有用于接收用于选择数据的选择器地址信号的第一输入单元，用于至少接收地址选通信号的第二输入单元，用于选择数据的X地址信号和Y地址信号 ; 用于接收X地址信号和Y地址信号的第一单元，利用第一时钟信号锁存这些信号，并连续输出X和Y地址信号中的至少一个，直到这些地址信号被解锁为止; 以及第二单元，用于使用所述第一时钟信号来锁存从所述第一输入单元输出的选择器地址数据信号，并且连续且选择性地输出所述地址信号中的至少一个，直到所述信号被解锁为止。 存储器系统操作以在正常操作模式和快速页模式下以适合流水线操作周期的方式传送数据。

    Semiconductor integrated circuit having logi gates
    5.
    发明授权
    Semiconductor integrated circuit having logi gates 失效
    具有逻辑门的半导体集成电路

    公开(公告)号：US5675548A

    公开(公告)日：1997-10-07

    申请号：US608605

    申请日：1996-02-29

    申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  G11C8/00

    CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

    摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

    摘要翻译： 提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端 信号，并且每个都耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 还提供了一种用于这种半导体存储器电路的改进的读/写布置，该电路包括用于在写入操作期间公共读取线与数据线的连接的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。

    Signal transition detector circuit
    6.
    发明授权
    Signal transition detector circuit 失效
    信号转换检测电路

    公开(公告)号：US5680066A

    公开(公告)日：1997-10-21

    申请号：US182699

    申请日：1994-01-13

    申请人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira Ide ,  Masahiro Yamamura ,  Hideaki Uchida

    发明人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira Ide ,  Masahiro Yamamura ,  Hideaki Uchida

    IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K5/1534 ,  H03K19/0175 ,  H03K5/153 ,  G01R29/02 ,  H03K3/033

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K19/017518 ,  H03K5/1534

    摘要： A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

    摘要翻译： 一种半导体器件，其包括以下中的至少一个：（1）由输入电平转换器和非反相缓冲电路构成的输入缓冲电路和各自包括实现高速操作的BiCMOS电路的反相缓冲电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路 具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变 并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据来自响应于ATD信号的时钟发生器的信号来控制诸如存储器的装置的解码器，读出放大器和输出缓冲器。

    Semiconductor integrated circuit having logic gates
    7.
    发明授权
    Semiconductor integrated circuit having logic gates 失效
    具有逻辑门的半导体集成电路

    公开(公告)号：US5387827A

    公开(公告)日：1995-02-07

    申请号：US643372

    申请日：1991-01-22

    申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  H03K19/23

    CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

    摘要： A semiconductor integrated logic circuit is provided which includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, wherein each of the logic gates is coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. This arrangement is particularly effective for decoders in semiconductor memory circuits which use a common NMOS to receive one input for a plurality of logic decoder gates. An improved read/write arrangement is also provided for semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

    摘要翻译： 提供了一种半导体集成逻辑电路，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入信号的第一输入端，其中每个逻辑门耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 这种布置对于使用公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效。 还提供了一种用于半导体存储器电路的改进的读/写布置，其包括在写入操作期间防止公共读取线连接到数据线的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。

    Semiconductor memory and microprocessor
    8.
    发明授权
    Semiconductor memory and microprocessor 失效
    半导体存储器和微处理器

    公开(公告)号：US5091883A

    公开(公告)日：1992-02-25

    申请号：US552100

    申请日：1990-07-13

    申请人： Nozomu Matsuzaki ,  Takashi Akioka ,  Masahiro Iwamura ,  Atushi Hiraishi ,  Tatsumi Yamauchi ,  Yuji Yokoyama ,  Yutaka Kobayashi ,  Hideaki Uchida

    发明人： Nozomu Matsuzaki ,  Takashi Akioka ,  Masahiro Iwamura ,  Atushi Hiraishi ,  Tatsumi Yamauchi ,  Yuji Yokoyama ,  Yutaka Kobayashi ,  Hideaki Uchida

    IPC分类号： G11C11/41 ,  G11C5/06 ,  G11C11/401 ,  G11C11/409 ,  H01L27/10

    CPC分类号： G11C5/063

    摘要： An input buffer for processing an external signal is provided in one of passways, which is the most closest to a line for equally dividing the whole of a plurality of memory cell blocks longitudinally or laterally into two sections, the passway interposing between the adjacent memory cell blocks of the plurality of memory cell blocks to which a processed signal of the input buffer is transmitted, whereby the length of the signal pass from the input buffer to each memory cell of the memory cell blocks can be shortened. Therefore, since the memory cell or a logic element existing between the input buffer and the memory cell is operated by a pulse of little distortion without delay of time, a access time can be reduced and a processing speed of a microprocessor can be increased. Further, a degree of freedom in designing a system of a memory or the microprocessor is further improved.

    摘要翻译： 用于处理外部信号的输入缓冲器被提供在通路中的一个通道中，该通道最靠近用于将多个存储单元块的整体纵向或横向均匀地分成两部分的通道，该通道插入相邻的存储单元 可以缩短输入缓冲器的经处理信号的多个存储单元块的块，从而可以缩短信号从输入缓冲器传递到存储单元块的每个存储单元的长度。 因此，由于存储单元或者存在于输入缓冲器和存储单元之间的逻辑单元在没有时间延迟的情况下由几个失真的脉冲进行操作，所以可以减少访问时间并且可以提高微处理器的处理速度。 此外，进一步提高了设计存储器或微处理器的系统的自由度。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US5619151A

    公开(公告)日：1997-04-08

    申请号：US473742

    申请日：1995-06-07

    申请人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira ide ,  Masahiro Yamamura ,  Hideaki Uchida

    发明人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira ide ,  Masahiro Yamamura ,  Hideaki Uchida

    IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K5/1534 ,  H03K19/0175 ,  H03K5/153 ,  G01R29/02 ,  H03K3/033

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K19/017518 ,  H03K5/1534

    摘要： A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

    摘要翻译： 一种半导体存储器件，包括以下中的至少一个：（1）响应于输入地址产生内部地址信号的输入缓冲器电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路 具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变 并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据响应于ATD信号的时钟发生器的信号来控制器件的解码器，读出放大器和输出缓冲器。

    Semiconductor integrated circuit having logic gates
    10.
    发明授权
    Semiconductor integrated circuit having logic gates 失效
    具有逻辑门的半导体集成电路

    公开(公告)号：US5544125A

    公开(公告)日：1996-08-06

    申请号：US383866

    申请日：1995-02-06

    申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  G11C8/00

    CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

    摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

    摘要翻译： 提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端 信号，并且每个都耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 还提供了一种改进的读/写布置，用于这样的半导体存储器电路，其包括在写入操作期间防止公共读取线与数据线连接的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。