公开(公告)号：US06252294B1

公开(公告)日：2001-06-26

申请号：US09438578

申请日：1999-11-12

申请人： Nobuyoshi Hattori ,  Hideki Naruoka ,  Hidekazu Yamamoto

发明人： Nobuyoshi Hattori ,  Hideki Naruoka ,  Hidekazu Yamamoto

IPC分类号： H01L2701

CPC分类号： H01L21/84 ,  H01L23/26 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S257/903 ,  Y10S257/913 ,  H01L2924/00

摘要： A semiconductor device and a semiconductor storage device having an SOI structure and being enable sufficient gettering performance without imposing limitations on the freedom of design of an LSI circuit. A semiconductor device includes a semiconductor wafer of SOI structure which has a insulation layer and a silicon layer provided thereon, wherein the semiconductor wafer includes a plurality of element fabrication regions where semiconductor elements are fabricated, and a cutting region provided between the element fabrication regions. Gettering sites are formed in the cutting region by means of embedding a gettering member into grooves of predetermined depth.

摘要翻译： 具有SOI结构的半导体器件和半导体存储器件，并且能够实现充分的吸杂性能，而不会对LSI电路的设计自由度施加限制。 半导体器件包括SOI结构的半导体晶片，其具有绝缘层和设置在其上的硅层，其中半导体晶片包括多个制造半导体元件的元件制造区域和设置在元件制造区域之间的切割区域。 通过将吸气构件嵌入到预定深度的凹槽中，在切割区域中形成吸气部位。

公开(公告)号：US06844242B2

公开(公告)日：2005-01-18

申请号：US10113291

申请日：2002-04-02

申请人： Hideki Naruoka ,  Nobuyoshi Hattori ,  Hidekazu Yamamoto

发明人： Hideki Naruoka ,  Nobuyoshi Hattori ,  Hidekazu Yamamoto

IPC分类号： H01L21/683 ,  H01L21/00 ,  H01L21/02 ,  H01L21/762 ,  H01L27/12 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L21/67092 ,  H01L21/76251 ,  Y10S414/138

摘要： A boat (4) has a recess (5) for supporting a laminated wafer (50). The recess (5) has a first side surface (5a), a first bottom surface (5b), a second side surface (5c), a second bottom surface (5d) and a third side surface (5e). Viewing from an upper surface of the boat (4), the second bottom surface (5d) is located in a position lower than the first bottom surface (5b). The laminated wafer (50) is mounted on the boat (4) in the state that a side surface of a first silicon wafer (1) is not in contact with the second bottom surface (5d) of the recess (5) and a side surface of a second silicon wafer (2) is in contact with the first bottom surface (5b) of the recess (5). A second main surface (2a) of the second silicon wafer (2) is in contact with the first side surface (5a) of the recess (5) and a second main surface (1a) of the first silicon wafer (1) is in contact with the third side surface (5e) of the recess (5).

摘要翻译： 船（4）具有用于支撑层叠晶片（50）的凹部（5）。 凹部（5）具有第一侧面（5a），第一底面（5b），第二侧面（5c），第二底面（5d）和第三侧面（5e）。 从船（4）的上表面看，第二底面（5d）位于比第一底面（5b）低的位置。 在第一硅晶片（1）的侧面与凹部（5）的第二底面（5d）不接触的状态下，将层叠晶片（50）安装在舟皿（4）上， 第二硅晶片（2）的表面与凹部（5）的第一底表面（5b）接触。 第二硅晶片（2）的第二主表面（2a）与凹部（5）的第一侧表面（5a）接触，并且第一硅晶片（1）的第二主表面（1a）处于 与凹部（5）的第三侧表面（5e）接触。

公开(公告)号：US06914307B2

公开(公告)日：2005-07-05

申请号：US10657068

申请日：2003-09-09

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L21/76286 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458

摘要： A semiconductor device includes a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, semiconductor elements being electrically isolated from each other by the isolation film. The semiconductor device also includes a PN junction portion provided under the isolation film and formed by two semiconductor regions of different conductivity types in the semiconductor layer. The isolation film includes a nitride film provided in a position corresponding to a top of the PN junction portion and has a substantially uniform thickness across the two semiconductor regions and an upper oxide film and a lower oxide film which are provided in upper and lower portions of the nitride film. The surface of the semiconductor layer is silicidized in such a state that a surface of the isolation film is exposed.

摘要翻译： 半导体器件包括半导体层，形成在半导体层上的多个半导体元件和设置在半导体层的表面中的隔离膜，半导体元件通过隔离膜彼此电隔离。 半导体器件还包括设置在隔离膜下方并由半导体层中由不同导电类型的两个半导体区域形成的PN结部分。 隔离膜包括设置在与PN结部分的顶部相对应的位置的氮化物膜，并且在两个半导体区域上具有基本上均匀的厚度，以及设置在上部和下部的上部氧化物膜和低级氧化物膜 氮化膜。 半导体层的表面在隔离膜的表面露出的状态下被硅化。

公开(公告)号：US06646306B2

公开(公告)日：2003-11-11

申请号：US09985020

申请日：2001-11-01

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

IPC分类号： H01L2701

CPC分类号： H01L21/76286 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458

摘要： A semiconductor device that prevents metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film, a polysilicon film selectively provided on the trench isolation oxide film, a silicon layer provided on the polysilicon film, and a side wall spacer provided on a side surface of the polysilicon film. The polysilicon film is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region and an N-type well region in a SOI layer across the two well regions.

摘要翻译： 一种防止金属污染的半导体器件以及半导体器件的制造方法。 区域（NR）和区域（PR）由沟槽隔离氧化膜，选择性地设置在沟槽隔离氧化膜上的多晶硅膜，设置在多晶硅膜上的硅层和设置在侧面上的侧壁隔离物 多晶硅膜的表面。 多晶硅膜设置在对应于跨越两个阱区域的SOI层中的P型阱区域和N型阱区域的PN结部分JP的顶部的位置。

公开(公告)号：US20050212056A1

公开(公告)日：2005-09-29

申请号：US11135522

申请日：2005-05-24

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786

CPC分类号： H01L21/76286 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458

摘要： To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.

摘要翻译： 提供能够防止金属污染引起的缺陷的半导体器件以及半导体器件的制造方法。 区域（NR）和区域（PR）由沟槽隔离氧化膜（ST21）限定，在沟槽隔离氧化膜（ST21）上选择性地设置多晶硅膜（PS21），硅层（S 22）设置在多晶硅膜（PS21）上，在多晶硅膜（PS21）的侧面设置有侧壁隔板（SW2）。 多晶硅膜（PS21）被设置在对应于SOI层3中的P型阱区域（WR 11）和N型阱区域（WR 12）的PN结部分JP的顶部的位置 两个井区。

公开(公告)号：US6016562A

公开(公告)日：2000-01-18

申请号：US919166

申请日：1997-08-28

申请人： Yoko Miyazaki ,  Nobuyoshi Hattori ,  Junko Izumitani ,  Masahiko Ikeno

发明人： Yoko Miyazaki ,  Nobuyoshi Hattori ,  Junko Izumitani ,  Masahiko Ikeno

IPC分类号： H01L21/66 ,  G01R31/01 ,  G01R31/28 ,  G06F11/10

CPC分类号： G01R31/01 ,  G01R31/2831 ,  H01L22/12

摘要： An ordinary user can easily learn a step at which a problem occurs during semiconductor manufacturing processes and improve the yield of manufacturing products and the quality of the products. At a certain in-line inspection step, a CPU (3) stores data signals (V1) taken by an inspection apparatus (1) into a memory (2), and reads a result (V6) obtained at a precedent step and stores the same in the memory (2). The CPU (3) reads stored data signals (V2) from the memory (2), performs comparison or referral on data about defects which are detected at a current step and the result (V6) regarding the precedent step, and generates a defect data analysis processing result signal (V5) regarding the current step. The result (V5) consists of disappeared defect data, common defect data, new defect data to which a label of a current step number is assigned, and reappeared defect data. The CPU (3) performs the processing above for each in-line inspection step, edits resultant data, and generates histogram data which provide the number of detected defects and the number of disappeared defects for each step.

摘要翻译： 普通用户可以轻松地学习在半导体制造过程中发生问题的步骤，并提高制造产品的产量和产品的质量。 在某个在线检查步骤中，CPU（3）将由检查装置（1）取得的数据信号（V1）存储到存储器（2）中，并读取在先前步骤获得的结果（V6） 在内存中相同（2）。 CPU（3）从存储器（2）读取存储的数据信号（V2），对与当前步骤检测到的缺陷有关的数据和关于先前步骤的结果（V6）进行比较或推荐，生成缺陷数据 关于当前步骤的分析处理结果信号（V5）。 结果（V5）由消失的缺陷数据，公共缺陷数据，分配了当前步骤编号的标签的新缺陷数据和重新出现的缺陷数据组成。 CPU（3）对于每个在线检查步骤执行上述处理，编辑结果数据，并且生成提供检测到的缺陷数量和每个步骤的消失缺陷数量的直方图数据。

公开(公告)号：US08242605B2

公开(公告)日：2012-08-14

申请号：US12795863

申请日：2010-06-08

申请人： Hiroyuki Arie ,  Nobuaki Umemura ,  Nobuyoshi Hattori ,  Nobuto Nakanishi ,  Kimio Hara ,  Kyoya Nitta ,  Makoto Ishikawa

发明人： Hiroyuki Arie ,  Nobuaki Umemura ,  Nobuyoshi Hattori ,  Nobuto Nakanishi ,  Kimio Hara ,  Kyoya Nitta ,  Makoto Ishikawa

IPC分类号： H01L23/48

CPC分类号： H01L29/7835 ,  H01L21/02057 ,  H01L21/743 ,  H01L29/4175 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.

摘要翻译： 在具有LDMOSFET的半导体器件中，源电极位于其后表面。 因此，为了降低顶表面的源极接触区域与后表面的源电极之间的电阻，提供了通过P型外延从上表面延伸到P +型衬底的多晶硅埋入式插塞 并用硼重掺杂。 在多晶硅埋塞塞周围的单晶硅区域发生位错，引起泄漏故障。 半导体器件具有延伸穿过具有不同杂质浓度的第一和第二半导体层之间的边界表面的硅基插塞。 至少插头的内部是多晶区域。 在多晶区域的表面中，位于与其相邻的上述边界面的两侧的部分各自被固相外延区域覆盖。

公开(公告)号：US07674668B2

公开(公告)日：2010-03-09

申请号：US12005444

申请日：2007-12-26

申请人： Norio Ishitsuka ,  Nobuyoshi Hattori ,  Tomio Iwasaki

发明人： Norio Ishitsuka ,  Nobuyoshi Hattori ,  Tomio Iwasaki

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.

摘要翻译： 在半导体衬底的主表面上形成栅电极之后，通过使用栅电极作为掩模，在半导体衬底的主表面上注入杂质，形成低浓度层。 此后，在栅电极的两个侧表面上形成第一侧壁和第二侧壁。 随后，使用第一侧壁，第二侧壁和栅电极作为掩模，将氮等离子注入到半导体衬底中，从而在半导体衬底的主表面上形成结晶化控制区域（CCR） 。 然后，在去除第二侧壁之后，在半导体衬底的主表面上形成用于源极和漏极的高浓度层。

公开(公告)号：US06473665B2

公开(公告)日：2002-10-29

申请号：US09920818

申请日：2001-08-03

申请人： Toshiaki Mugibayashi ,  Nobuyoshi Hattori

发明人： Toshiaki Mugibayashi ,  Nobuyoshi Hattori

IPC分类号： G06F1900

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle around (1)} non-defective chip with no new defect; {circle around (2)} defective chip with no new defect; {circle around (3)} non-defective chip with new defect; and {circle around (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.

公开(公告)号：US06341241B1

公开(公告)日：2002-01-22

申请号：US09206150

申请日：1998-12-07

申请人： Toshiaki Mugibayashi ,  Nobuyoshi Hattori

发明人： Toshiaki Mugibayashi ,  Nobuyoshi Hattori

IPC分类号： G06F1900

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle around (1)} non-defective chip with no new defect; {circle around (2)} defective chip with no new defect; {circle around (3)} non-defective chip with new defect; and {circle around (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.

摘要翻译： 缺陷分析方法可以定量地掌握单个过程的新缺陷数量对器件产量的影响。 在每个芯片中由于指定的处理而存在或不存在新缺陷之后，通过电测试器判断芯片的缺陷性或非缺陷性，将晶片上的多个芯片分为四组：{ 圆（1）}无缺陷芯片无新缺陷; {圈（2）}缺陷芯片没有新的缺陷; {圈（3）}无缺陷芯片新缺陷; 和{圈绕（4）}缺陷芯片有新的缺陷，以获得仅由指定过程的新缺陷引起的新的有缺陷的芯片的数量; 芯片被认为有缺陷的指定工艺的新缺陷的临界比率; 以及被认为是由指定处理引起的处理有缺陷的芯片的数量。