公开(公告)号：US20080203403A1

公开(公告)日：2008-08-28

申请号：US11960680

申请日：2007-12-19

申请人： Takayuki Kawahara ,  Masanao Yamaoka ,  Nobuyuki Sugii

发明人： Takayuki Kawahara ,  Masanao Yamaoka ,  Nobuyuki Sugii

IPC分类号： H01L33/00 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1203 ,  H01L27/153

摘要： The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under UTB, to which a voltage can be applied independently of a corresponding gate terminal. The logic circuit includes an nMOS (7) and a pMOS (8), and both are of a fully-depleted type, formed on UTB and have an SOI structure. The fully-depleted type nMOS and pMOS have backgate regions (14, 22) under respective UTBs, to which voltages can be applied independently of the corresponding gate terminals

摘要翻译： 半导体集成电路（1）具有在硅衬底（2）上混合堆垛的存储器（4）和逻辑电路（5）。 存储器包括具有SOI结构并形成在UTB（3）上的部分耗尽型nMOS（6）。 部分耗尽型nMOS在UTB之下具有背栅区域（14），独立于对应的栅极端子可以施加电压。 逻辑电路包括nMOS（7）和pMOS（8），并且它们都是完全耗尽型的，形成在UTB上并具有SOI结构。 完全耗尽型nMOS和pMOS在相应的UTB下具有背栅区域（14,22），可以独立于对应的栅极端子施加电压

公开(公告)号：US20110188329A1

公开(公告)日：2011-08-04

申请号：US13086377

申请日：2011-04-13

申请人： Takayuki Kawahara ,  Masanao Yamaoka ,  Nobuyuki Sugii

发明人： Takayuki Kawahara ,  Masanao Yamaoka ,  Nobuyuki Sugii

IPC分类号： G11C7/00 ,  H01L27/088

CPC分类号： H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1203 ,  H01L27/153

摘要： The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under UTB, to which a voltage can be applied independently of a corresponding gate terminal. The logic circuit includes an nMOS (7) and a pMOS (8), and both are of a fully-depleted type, formed on UTB and have an SOI structure. The fully-depleted type nMOS and pMOS have backgate regions (14, 22) under respective UTBs, to which voltages can be applied independently of the corresponding gate terminals

摘要翻译： 半导体集成电路（1）具有在硅衬底（2）上混合堆垛的存储器（4）和逻辑电路（5）。 存储器包括具有SOI结构并形成在UTB（3）上的部分耗尽型nMOS（6）。 部分耗尽型nMOS在UTB之下具有背栅区域（14），独立于对应的栅极端子可以施加电压。 逻辑电路包括nMOS（7）和pMOS（8），并且它们都是完全耗尽型的，形成在UTB上并具有SOI结构。 完全耗尽型nMOS和pMOS在相应的UTB下具有背栅区域（14,22），可以独立于对应的栅极端子施加电压

公开(公告)号：US08183635B2

公开(公告)日：2012-05-22

申请号：US12756451

申请日：2010-04-08

申请人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Shinichiro Kimura ,  Takashi Ishigaki ,  Yusuke Morita ,  Hiroyuki Yoshimoto

发明人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Shinichiro Kimura ,  Takashi Ishigaki ,  Yusuke Morita ,  Hiroyuki Yoshimoto

IPC分类号： H01L21/00

CPC分类号： H01L27/1203 ,  H01L21/76283

摘要： A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

摘要翻译： 通过改善在SOI衬底的浅沟槽和SOI层的边界部分的形状来实现低功耗的半导体器件的技术。 硅衬底的主表面和沿着SOI层的侧表面延伸的线交叉的位置（SOI边缘）比浅沟槽隔离更远离位于（STI边缘）的位置（STI边缘），在该位置处 沿着浅沟槽的侧壁延伸并且沿着硅衬底的主表面延伸的线交叉，并且在STI边缘处的硅衬底的拐角具有弯曲表面。

公开(公告)号：US20100258871A1

公开(公告)日：2010-10-14

申请号：US12759559

申请日：2010-04-13

申请人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii

发明人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.

摘要翻译： 具有FINFET的半导体器件的特性得到改善。 FINFET具有：在半导体衬底上以拱形形式布置并由单晶硅形成的沟道层; 前栅电极，其通过前栅极绝缘膜形成在沟道层的外部的一部分上; 以及形成为通过背栅绝缘膜埋设在沟道层内的背栅电极。 布置在拱形内侧的背栅极布置成穿过前栅电极。

公开(公告)号：US20080111134A1

公开(公告)日：2008-05-15

申请号：US11969488

申请日：2008-01-04

申请人： Shinya Yamaguchi ,  Masanobu Miyao ,  Nobuyuki Sugii ,  Seang-kee Park ,  Kiyokazu Nakagawa

发明人： Shinya Yamaguchi ,  Masanobu Miyao ,  Nobuyuki Sugii ,  Seang-kee Park ,  Kiyokazu Nakagawa

IPC分类号： H01L29/10 ,  H01L21/00

CPC分类号： H01L29/78696 ,  G09G3/3648 ,  G09G2300/0408 ,  H01L27/1277 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/045 ,  H01L29/41733 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78666 ,  H01L29/78669 ,  H01L29/78675 ,  H01L29/78678

摘要： To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.

摘要翻译： 为了提供具有较高电子迁移率的改进的低温多晶层的TFT，并且鉴于通过利用玻璃基板实现具有大的显示面积的液晶显示装置，确保制造中的波动较小。 通过利用与金刚石结构的{111}双边界结合的多晶晶粒形成的半导体薄膜（称为准单晶薄膜），可以在特定波动的预定范围内实现具有较高电子迁移率的TFT 作为TFT的沟道区域（即有源区）。

公开(公告)号：US20060073664A1

公开(公告)日：2006-04-06

申请号：US11242961

申请日：2005-10-05

申请人： Masao Kondo ,  Nobuyuki Sugii ,  Yoshinobu Kimura

发明人： Masao Kondo ,  Nobuyuki Sugii ,  Yoshinobu Kimura

IPC分类号： H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66659

摘要： Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1×1019 cm−3 or less.

摘要翻译： 提供了能够抑制形成在应变硅层中的沟道区域中的电子迁移率降低的技术。 在半导体衬底上形成的p型硅 - 锗层上形成p型应变硅层。 p型应变层的厚度被调整为比没有失配位错发生的临界膜厚度更厚。 因此，在p型应变硅层和p型硅 - 锗层之间的界面附近发生失配位错。 在位于栅电极末端并发生失配位错的位置处，n型应变硅层和n型硅 - 锗层的杂质浓度为1×10 19 cm -3， -3以下。

公开(公告)号：US06903372B1

公开(公告)日：2005-06-07

申请号：US09698274

申请日：2000-10-30

申请人： Shinya Yamaguchi ,  Masanobu Miyao ,  Nobuyuki Sugii ,  Seang-kee Park ,  Kiyokazu Nakagawa

发明人： Shinya Yamaguchi ,  Masanobu Miyao ,  Nobuyuki Sugii ,  Seang-kee Park ,  Kiyokazu Nakagawa

IPC分类号： G02F1/136 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/417 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/78696 ,  G09G3/3648 ,  G09G2300/0408 ,  H01L27/1277 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/045 ,  H01L29/41733 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78666 ,  H01L29/78669 ,  H01L29/78675 ,  H01L29/78678

摘要： To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate.A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.

摘要翻译： 为了提供具有较高电子迁移率的改进的低温多晶层的TFT，并且鉴于通过利用玻璃基板实现具有大的显示面积的液晶显示装置，确保制造中的波动较小。 通过利用与金刚石结构的{111}双边界结合的多晶晶粒形成的半导体薄膜（称为准单晶薄膜），可以在特定波动的预定范围内实现具有较高电子迁移率的TFT 作为TFT的沟道区域（即有源区）。

公开(公告)号：US06897129B2

公开(公告)日：2005-05-24

申请号：US10440102

申请日：2003-05-19

申请人： Yasuichi Kondo ,  Wataru Hirasawa ,  Nobuyuki Sugii

发明人： Yasuichi Kondo ,  Wataru Hirasawa ,  Nobuyuki Sugii

IPC分类号： C23C16/42 ,  C23C16/44 ,  C23C16/455 ,  C30B25/00 ,  H01L21/20 ,  H01L21/205 ,  H01L29/78

CPC分类号： C23C16/45506 ,  C23C16/22 ,  C23C16/45523 ,  C23C16/45563 ,  C23C16/45578 ,  C23C16/4584 ,  C23C16/46 ,  C30B25/00 ,  C30B25/02 ,  C30B29/403 ,  C30B29/52 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2807 ,  H01L29/1054 ,  H01L29/66575 ,  H01L29/78

摘要： Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.

公开(公告)号：US20050032327A1

公开(公告)日：2005-02-10

申请号：US10936684

申请日：2004-09-09

申请人： Kazuhiro Ohnishi ,  Nobuyuki Sugii ,  Takahiro Onai

发明人： Kazuhiro Ohnishi ,  Nobuyuki Sugii ,  Takahiro Onai

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/7833

摘要： A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.

公开(公告)号：US06815707B2

公开(公告)日：2004-11-09

申请号：US10259396

申请日：2002-09-30

申请人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

IPC分类号： H01L2904

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/7835 ,  H03F3/601 ,  Y10S438/933

摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

摘要翻译： 在具有第一导电型和高杂质浓度的第一SiGe层的半导体多层结构中，形成具有第一导电型和低杂质浓度的第二SiGe层和具有低杂质浓度的Si层 在第一导电类型的Si衬底上依次另一个，在Si层的一部分中形成沟道，并且源极通过低杂质浓度的第二SiGe层，以电接触第一SiGe层的第一SiGe层 高杂质浓度或底物。