公开(公告)号：US4985743A

公开(公告)日：1991-01-15

申请号：US221354

申请日：1988-07-19

申请人： Norihito Tokura ,  Hiroyasu Ito ,  Naoto Okabe

发明人： Norihito Tokura ,  Hiroyasu Ito ,  Naoto Okabe

IPC分类号： H01L29/78 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/68 ,  H01L29/739

CPC分类号： H01L29/0847 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/7395

摘要： This invention is basically related to an insulated gate bipolar transistor comprising a first conductivity type semiconductor substrate, a second conductivity type semiconductor layer formed on the substrate and having a low concentration of impurities, a first conductivity type base layer formed on a surface of the semiconductor layer, a second conductivity type source layer formed on the surface of the base layer and having a channel region at at least one end thereof, a gate electrode, a source electrode and a drain electrode, and is characterized in that a voltage dropping portion is provided either inside the source layer or between the source layer and the source electrode. Accordingly an insulated gate bipolar semiconductor transistor having this configuration can prevent a latch up phenomenon caused by a voltage drop in a source layer.

摘要翻译： 本发明基本上涉及一种包括第一导电类型半导体衬底，形成在衬底上并具有低浓度杂质的第二导电类型半导体层的绝缘栅双极晶体管，形成在半导体表面上的第一导电型基极层 层，形成在基层的表面上并在其至少一端具有沟道区的第二导电型源极层，栅电极，源电极和漏电极，其特征在于，降压部分为 提供在源层内部或源层和源电极之间。 因此，具有这种结构的绝缘栅双极半导体晶体管可以防止由源极层中的电压降引起的闭锁现象。

公开(公告)号：US5753943A

公开(公告)日：1998-05-19

申请号：US612285

申请日：1996-03-07

申请人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

发明人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/322 ,  H01L21/331 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739 ,  H01L29/749

CPC分类号： H01L29/66333 ,  H01L21/3221 ,  H01L29/0834 ,  H01L29/7395 ,  Y10S257/913

摘要： In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

公开(公告)号：US6146947A

公开(公告)日：2000-11-14

申请号：US54493

申请日：1998-04-03

申请人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

发明人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/322 ,  H01L21/331 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739

CPC分类号： H01L29/66333 ,  H01L21/3221 ,  H01L29/0834 ,  H01L29/7395 ,  Y10S257/913

摘要： In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

摘要翻译： 在绝缘栅型场效应晶体管及其制造方法中，通过热扩散在氧化气氛下在半导体衬底中形成扩散区，并且通过气相在半导体衬底上形成第一导电类型半导体层 形成扩散区后的外延。 此后，半导体层的表面变平，在平坦的半导体层上形成栅极绝缘膜和栅电极。 此外，在半导体层中形成阱区以及源极区，形成绝缘栅型场效应晶体管。 由于形成绝缘栅型场效应晶体管的半导体层的表面平坦化，即使在晶片中形成嵌入区域，也可以防止栅源绝缘耐压特性劣化。

公开(公告)号：US5519245A

公开(公告)日：1996-05-21

申请号：US56946

申请日：1993-05-05

申请人： Norihito Tokura ,  Naoto Okabe ,  Naohito Kato

发明人： Norihito Tokura ,  Naoto Okabe ,  Naohito Kato

IPC分类号： H01L29/08 ,  H01L29/739 ,  H01L29/80 ,  H01L23/58 ,  H01L29/76 ,  H01L29/861

CPC分类号： H01L29/0834 ,  H01L29/7395 ,  H01L2924/0002

摘要： An insulated gate bipolar transistor has a reverse conducting function built therein. A semiconductor layer of a first conduction type is formed on the side of a drain, a semiconductor layer of a second conduction type for causing conductivity modulation upon carrier injection is formed on the semiconductor layer of the first conduction type, a semiconductor layer of the second conduction type for taking out a reverse conducting current opposite in direction to a drain current is formed in the semiconductor layer of the second conduction type which is electrically connected to a drain electrode, and a semiconductor layer of the second conduction type is formed at or in the vicinity of a pn junction, through which carriers are given and received to cause conductivity modulation, with a high impurity concentration resulting in a path for the reverse conducting current into a pattern not impeding the passage of the carriers. Therefore, the built-in reverse conducting function has a low operating resistance, a large reverse current can be passed, there is no increase in on-resistance, and the turn-off time can be shortened.

摘要翻译： 绝缘栅双极晶体管内置有反向导通功能。 第一导电类型的半导体层形成在漏极侧，在第一导电类型的半导体层上形成用于在载流子注入时引起导电性调制的第二导电类型的半导体层，第二导电类型的半导体层 在与漏电极电连接的第二导电类型的半导体层中形成用于取出与漏电流方向相反的反向导通电流的导通型，并且在第二导电类型的半导体层中形成第二导电类型的半导体层 pn结的附近，赋予和接收载流子以引起电导率调制的pn结附近，杂质浓度高，导致反向导通电流进入不妨碍载流子通过的图案的路径。 因此，内置的反向导通功能具有低的工作电阻，可以通过大的反向电流，导通电阻不增加，并且可以缩短关断时间。

公开(公告)号：US5973338A

公开(公告)日：1999-10-26

申请号：US947402

申请日：1997-10-08

申请人： Naoto Okabe ,  Norihito Tokura ,  Naohito Kato

发明人： Naoto Okabe ,  Norihito Tokura ,  Naohito Kato

IPC分类号： H01L29/68 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/1095 ,  H01L29/7395

摘要： An insulated gate type bipolar-transistor (IGBT) incorporates an excess voltage protecting function and drain voltage fixing function in a monolithic structure. Impurity concentration ND and the thickness of an n.sup.- type drain layer (3) is set so that a depletion region propagating from a p type base layer (7) reaches a p.sup.+ type drain layer at a voltage (V.sub.DSP) lower than a voltage (V.sub.DSS) at which avalanche breakdown is caused within the IGBT element when voltage is applied between the source and the drain.

摘要翻译： 绝缘栅型双极晶体管（IGBT）在整体结构中包含过电压保护功能和漏极电压固定功能。 杂质浓度ND和n型漏极层（3）的厚度被设定为使得从ap型基极层（7）传播的耗尽区域在低于电压（VDSS）的VDSP下达到p +型漏极层 ），当在源极和漏极之间施加电压时，在IGBT元件内引起雪崩击穿。

公开(公告)号：US5448092A

公开(公告)日：1995-09-05

申请号：US70362

申请日：1993-06-01

申请人： Naoto Okabe ,  Norihito Tokura

发明人： Naoto Okabe ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L27/04 ,  H01L29/10 ,  H01L29/739 ,  H01L29/76 ,  H01L29/00 ,  H01L29/74

CPC分类号： H01L29/7395 ,  H01L27/0248 ,  H01L29/1095

摘要： An insulated gate bipolar transistor (IGBT) element has a current detection function. An impurity-diffused area is formed at an area different from a unit cell area on the surface of the element. The current detection is performed by detecting a voltage drop due to carriers flowing in the lateral resistance of the impurity-diffused area. For example, in an n-channel IGBT, electrons are injected from a source electrode through an n-type source layer and the channel to an n-type drain layer at the cell when the unit cell is in an on-state. The pn junction at the drain side is forwardly biased to inject holes from the p-type drain layer to the n-type drain layer. At this time, the electrons also flow to the lower side of the p-type impurity-diffused area provided as the detection portion. Thus, the hole injection occurs at this portion. These surplus holes are discharged through the p-type layer of the detection portion to the source electrode. A potential which corresponds to a product of the lateral resistance of the p-type layer and a hole current appears at the source potential. By detecting this potential and converting the detected potential, an element current can be detected.

摘要翻译： PCT No.PCT / JP92 / 01239 Sec。 371日期：1993年6月1日 102（e）日期1993年6月1日PCT 1992年9月28日PCT公布。 出版物WO93 / 07645 日期：1993年04月15日。绝缘栅双极晶体管（IGBT）元件具有电流检测功能。 在与元件表面上的单元电池区域不同的区域上形成杂质扩散区域。 通过检测由于在杂质扩散区域的横向电阻中流动的载流子的电压降而进行电流检测。 例如，在n沟道IGBT中，当单位电池处于导通状态时，电子从源电极通过n型源极层和沟道注入到单元的n型漏极层。 漏极侧的pn结被向前偏置以从p型漏极层向n型漏极层注入空穴。 此时，电子也流到作为检测部设置的p型杂质扩散区域的下侧。 因此，在该部分发生空穴注入。 这些剩余的孔通过检测部的p型层被排出到源电极。 对应于p型层的横向电阻和空穴电流的乘积的电位出现在电位电位。 通过检测该电位并转换检测到的电位，可以检测元件电流。

公开(公告)号：US5169793A

公开(公告)日：1992-12-08

申请号：US710721

申请日：1991-06-07

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Naohito Kato

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Naohito Kato

IPC分类号： H01L21/8234 ,  H01L21/331 ,  H01L27/088 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/66333 ,  H01L29/1095

摘要： A p type pad well layer is formed at the surface of an n.sup.- type drain layer under a gate bonding pad and the surface thereof is provided with a p.sup.++ type pad layer to be provided with lower resistivity. The p.sup.++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, the introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p.sup.++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p.sup.++ type pad layer can be easily formed. The p.sup.++ type pad layer serves as a low resistance path for allowing the holes flowing into the region under the pad region of the insulated gate bipolar transistor to escape to the source electrode, whereby occurrence of the latch up and increase in the turn-off time due to the minority carriers concentrating into the border portion cell located adjacent to the pad region can be prevented.

摘要翻译： p型衬垫阱层形成在栅极焊盘下方的n型漏极层的表面处，并且其表面设置有具有较低电阻率的p ++型焊盘层。 p ++型垫层通过接触孔与源电极连接。 由于向每个单元提供栅极电位的栅极电极具有沿着焊盘区域和单元区域之间的边界布置的梳齿形式的延伸的图案，所以在焊盘下面基本上不存在栅电极。 因此，在形成栅电极之后，可以在形成p ++型接触层的同时进行在焊盘区域下方的阱层的整个表面的杂质的引入，因此，低电阻p ++型焊盘层可以容易地 形成。 p ++型衬垫层用作低电阻路径，用于允许流入绝缘栅双极晶体管的焊盘区域下方的空穴逸出到源电极，由此发生闭锁并增加关断时间 由于可以防止集中在位于焊盘区域附近的边界部分单元的少数载流子。

公开(公告)号：US6107661A

公开(公告)日：2000-08-22

申请号：US720018

申请日：1996-09-27

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/7809

摘要： A concave channel type DMOS structure having an improved gate-to-source breakdown voltage are disclosed. By establishing a curvature at a corner portion of a lattice-like pattern in a groove portion for forming the concave channel structure, the shape of the tip of a three-dimensionally projecting portion of a semiconductor region determined by a plane angle of the corner portion in the lattice-like pattern and an inclination of the groove portion is rounded. That is, a three-dimensionally sharpened corner portion in the concave channel structure is rounded, and thereby electric field concentration at the corner portion is suppressed.

摘要翻译： 公开了具有改善的栅 - 源击穿电压的凹沟道型DMOS结构。 通过在用于形成凹槽结构的凹槽部分中的格子状图案的角部处建立曲率，由角部分的平面角确定的半导体区域的三维突出部分的尖端的形状 呈格子状，槽部的倾斜为圆形。 也就是说，凹槽结构中的三维锐角部分是圆形的，从而抑制角部处的电场集中。

公开(公告)号：US5464992A

公开(公告)日：1995-11-07

申请号：US358983

申请日：1994-12-19

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Naohito Kato

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Naohito Kato

IPC分类号： H01L21/8234 ,  H01L21/331 ,  H01L27/088 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L27/01 ,  H01L33/00

CPC分类号： H01L29/66333 ,  H01L29/1095

摘要： A p type pad well layer is formed at the surface of an n.sup.- type drain layer under a gate bonding pad and the surface thereof is provided with a p.sup.++ type pad layer to be provided with lower resistivity. The p.sup.++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p.sup.++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p.sup.++ type pad layer can be easily formed. The p.sup.++ type pad layer serves as a low resistance path for allowing the holes flowing into the region under the pad region of the insulated gate bipolar transistor to escape to the source electrode, whereby occurrence of the latch up and increase in the turn-off time due to the minority carriers concentrating into the border portion cell located adjacent to the pad region can be prevented.

摘要翻译： p型衬垫阱层形成在栅极焊盘下方的n型漏极层的表面处，并且其表面设置有具有较低电阻率的p ++型焊盘层。 p ++型垫层通过接触孔与源电极连接。 由于向每个单元提供栅极电位的栅极电极具有沿着焊盘区域和单元区域之间的边界布置的梳齿形式的延伸的图案，所以在焊盘下面基本上不存在栅电极。 因此，在形成栅极电极之后，可以在形成p ++型接触层的同时进行在焊盘区域下方的阱层的整个表面的杂质的引入，因此能够容易地形成低电阻p ++型焊盘层 。 p ++型衬垫层用作低电阻路径，用于允许流入绝缘栅双极晶体管的焊盘区域下方的空穴逸出到源电极，由此发生闭锁并增加关断时间 由于可以防止集中在位于焊盘区域附近的边界部分单元的少数载流子。

公开(公告)号：US06452219B1

公开(公告)日：2002-09-17

申请号：US08917488

申请日：1997-08-26

申请人： Yoshiyuki Miyase ,  Naohito Kato ,  Haruo Kawakita ,  Naoto Okabe

发明人： Yoshiyuki Miyase ,  Naohito Kato ,  Haruo Kawakita ,  Naoto Okabe

IPC分类号： H01L2974

CPC分类号： H01L29/66333 ,  H01L29/1095 ,  H01L29/7395 ,  Y10S257/913

摘要： An IGBT having a buffer layer for shortening the turn-off time and for preventing the latching up is improved. The buffer layer of the present invention is not bare at the edge of a diced cross-section of the IGBT chip. According to this construction, a withstanding voltage between a semiconductor substrate and the buffer layer is lower than the withstand voltage of the pn junction at the edge of the diced cross-section. Therefore, the whole pn junction between the semiconductor substrate and the buffer layer, which has wide area, breaks down, as a result, energy caused by a negative voltage is absorbed, and the withstanding voltage against the negative voltage is improved.

摘要翻译： 具有用于缩短关断时间和防止闭锁的缓冲层的IGBT得到改善。 本发明的缓冲层在IGBT芯片的切割截面的边缘处不裸露。 根据这种结构，半导体衬底和缓冲层之间的耐电压低于切割截面边缘处的pn结的耐电压。 因此，半导体衬底与具有宽面积的缓冲层之间的整个pn结被分解，结果，由负电压引起的能量被吸收，并且抵抗负电压的耐受电压提高。