公开(公告)号：US06452219B1

公开(公告)日：2002-09-17

申请号：US08917488

申请日：1997-08-26

申请人： Yoshiyuki Miyase ,  Naohito Kato ,  Haruo Kawakita ,  Naoto Okabe

发明人： Yoshiyuki Miyase ,  Naohito Kato ,  Haruo Kawakita ,  Naoto Okabe

IPC分类号： H01L2974

CPC分类号： H01L29/66333 ,  H01L29/1095 ,  H01L29/7395 ,  Y10S257/913

摘要： An IGBT having a buffer layer for shortening the turn-off time and for preventing the latching up is improved. The buffer layer of the present invention is not bare at the edge of a diced cross-section of the IGBT chip. According to this construction, a withstanding voltage between a semiconductor substrate and the buffer layer is lower than the withstand voltage of the pn junction at the edge of the diced cross-section. Therefore, the whole pn junction between the semiconductor substrate and the buffer layer, which has wide area, breaks down, as a result, energy caused by a negative voltage is absorbed, and the withstanding voltage against the negative voltage is improved.

摘要翻译： 具有用于缩短关断时间和防止闭锁的缓冲层的IGBT得到改善。 本发明的缓冲层在IGBT芯片的切割截面的边缘处不裸露。 根据这种结构，半导体衬底和缓冲层之间的耐电压低于切割截面边缘处的pn结的耐电压。 因此，半导体衬底与具有宽面积的缓冲层之间的整个pn结被分解，结果，由负电压引起的能量被吸收，并且抵抗负电压的耐受电压提高。

公开(公告)号：US4994880A

公开(公告)日：1991-02-19

申请号：US412552

申请日：1989-09-25

申请人： Naohito Kato ,  Yoshiyuki Miyase ,  Tomoatsu Makino ,  Kasuhiro Yamada ,  Masami Yamaoka ,  Takeshi Matsui ,  Masahiro Yamamoto ,  Yoshiki Ishida ,  Tohru Nomura

发明人： Naohito Kato ,  Yoshiyuki Miyase ,  Tomoatsu Makino ,  Kasuhiro Yamada ,  Masami Yamaoka ,  Takeshi Matsui ,  Masahiro Yamamoto ,  Yoshiki Ishida ,  Tohru Nomura

IPC分类号： H01L29/72 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/0692 ,  H01L29/41708

摘要： Base regions of first and second stage transistors are formed in a semiconductor substrate consisting of low and high resistivity collector layers, and emitter regions are formed in the respective base regions. The emitter region of the second stage transistor has an interdigital structure with a plurality of finger portions, and an emitter surface electrode is formed on the emitter region of the second stage transistor. The second stage transistor emitter surface electrode has an extending portion at a position spaced apart from a transistor operation region where the finger portions are formed. An emitter connection electrode is formed on the extending portion, and a lead is connected by soldering or the like to the emitter connection electrode. In a portion of the emitter surface electrode extending from the emitter connection electrode to the transistor operation region, slits are formed such that they are bypassed by emitter current so that the lead resistance from each finger portion to the emitter connection electrode is substantially uniform.

摘要翻译： 第一和第二级晶体管的基极区域形成在由低和高电阻率集电极层组成的半导体衬底中，并且发射极区域形成在各个基极区域中。 第二级晶体管的发射极区域具有多个指状部分的叉指结构，并且发射极表面电极形成在第二级晶体管的发射极区域上。 第二级晶体管发射体表面电极在与形成指状部分的晶体管工作区间隔开的位置处具有延伸部分。 发射极连接电极形成在延伸部分上，引线通过焊接等连接到发射极连接电极。 在从发射极连接电极延伸到晶体管工作区域的发射体表面电极的一部分中，形成狭缝，使得它们被发射极电流旁路，使得从每个指状部分到发射极连接电极的引线电阻基本上均匀。

公开(公告)号：US5169793A

公开(公告)日：1992-12-08

申请号：US710721

申请日：1991-06-07

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Naohito Kato

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Naohito Kato

IPC分类号： H01L21/8234 ,  H01L21/331 ,  H01L27/088 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/66333 ,  H01L29/1095

摘要： A p type pad well layer is formed at the surface of an n.sup.- type drain layer under a gate bonding pad and the surface thereof is provided with a p.sup.++ type pad layer to be provided with lower resistivity. The p.sup.++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, the introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p.sup.++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p.sup.++ type pad layer can be easily formed. The p.sup.++ type pad layer serves as a low resistance path for allowing the holes flowing into the region under the pad region of the insulated gate bipolar transistor to escape to the source electrode, whereby occurrence of the latch up and increase in the turn-off time due to the minority carriers concentrating into the border portion cell located adjacent to the pad region can be prevented.

摘要翻译： p型衬垫阱层形成在栅极焊盘下方的n型漏极层的表面处，并且其表面设置有具有较低电阻率的p ++型焊盘层。 p ++型垫层通过接触孔与源电极连接。 由于向每个单元提供栅极电位的栅极电极具有沿着焊盘区域和单元区域之间的边界布置的梳齿形式的延伸的图案，所以在焊盘下面基本上不存在栅电极。 因此，在形成栅电极之后，可以在形成p ++型接触层的同时进行在焊盘区域下方的阱层的整个表面的杂质的引入，因此，低电阻p ++型焊盘层可以容易地 形成。 p ++型衬垫层用作低电阻路径，用于允许流入绝缘栅双极晶体管的焊盘区域下方的空穴逸出到源电极，由此发生闭锁并增加关断时间 由于可以防止集中在位于焊盘区域附近的边界部分单元的少数载流子。

公开(公告)号：US5464992A

公开(公告)日：1995-11-07

申请号：US358983

申请日：1994-12-19

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Naohito Kato

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Naohito Kato

IPC分类号： H01L21/8234 ,  H01L21/331 ,  H01L27/088 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L27/01 ,  H01L33/00

CPC分类号： H01L29/66333 ,  H01L29/1095

摘要： A p type pad well layer is formed at the surface of an n.sup.- type drain layer under a gate bonding pad and the surface thereof is provided with a p.sup.++ type pad layer to be provided with lower resistivity. The p.sup.++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p.sup.++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p.sup.++ type pad layer can be easily formed. The p.sup.++ type pad layer serves as a low resistance path for allowing the holes flowing into the region under the pad region of the insulated gate bipolar transistor to escape to the source electrode, whereby occurrence of the latch up and increase in the turn-off time due to the minority carriers concentrating into the border portion cell located adjacent to the pad region can be prevented.

摘要翻译： p型衬垫阱层形成在栅极焊盘下方的n型漏极层的表面处，并且其表面设置有具有较低电阻率的p ++型焊盘层。 p ++型垫层通过接触孔与源电极连接。 由于向每个单元提供栅极电位的栅极电极具有沿着焊盘区域和单元区域之间的边界布置的梳齿形式的延伸的图案，所以在焊盘下面基本上不存在栅电极。 因此，在形成栅极电极之后，可以在形成p ++型接触层的同时进行在焊盘区域下方的阱层的整个表面的杂质的引入，因此能够容易地形成低电阻p ++型焊盘层 。 p ++型衬垫层用作低电阻路径，用于允许流入绝缘栅双极晶体管的焊盘区域下方的空穴逸出到源电极，由此发生闭锁并增加关断时间 由于可以防止集中在位于焊盘区域附近的边界部分单元的少数载流子。

公开(公告)号：US5723882A

公开(公告)日：1998-03-03

申请号：US401506

申请日：1995-03-10

申请人： Naoto Okabe ,  Naohito Kato

发明人： Naoto Okabe ,  Naohito Kato

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L29/76 ,  H01L23/58

CPC分类号： H01L29/7802 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/7395 ,  H01L29/0619 ,  H01L2924/0002

摘要： An insulated gate field effect transistor comprising a semiconductor substrate having one side on which a cell area is composed of a plurality of first wells of a first conductivity type, each of the first wells containing a source region of a second conductivity type. A channel region is defined in the surface portion of the semiconductor substrate adjoining to the source region, and a gate electrode is formed, via a gate insulating film, at least over the channel region. A source electrode is in common contact with the respective source regions of the plurality of first wells. The semiconductor substrate has a drain electrode provided on another side. A current flows between the source electrode and the drain electrode through the channel being controlled by a voltage applied to the gate electrode. A guard ring area is disposed on the one side of the semiconductor substrate so as to surround the cell area. The source electrode has an extension connected to a second well of a second conductivity type formed in the one side between the cell area and the guard ring area to provide a by-pass such that, when a current concentration occurs within the guard ring area, the concentrated current is conducted directly to the source electrode in the cell area through the by-pass, thereby preventing the concentrated current from causing a forward biassing between the first wells and the source region.

摘要翻译： 一种绝缘栅场效应晶体管，包括半导体衬底，所述半导体衬底具有一个单元面积由多个第一导电类型的第一阱组成的第一阱，每个第一阱包含第二导电类型的源极区。 在与源极区域相邻的半导体衬底的表面部分中限定沟道区，并且通过栅极绝缘膜至少在沟道区上形成栅电极。 源电极与多个第一阱的各个源极区共同接触。 半导体衬底具有设置在另一侧的漏电极。 A电流通过通过施加到栅电极的电压控制的沟道在源电极和漏电极之间流动。 保护环区域设置在半导体衬底的一侧，以围绕电池区域。 源电极具有连接到形成在电池区域和保护环区域之间的一侧中的第二导电类型的第二阱的延伸部，以提供旁路，使得当在保护环区域内发生电流集中时， 集中电流通过旁路直接传导到电池区域中的源电极，从而防止集中电流在第一阱和源极区域之间引起正向偏压。

公开(公告)号：US5519245A

公开(公告)日：1996-05-21

申请号：US56946

申请日：1993-05-05

申请人： Norihito Tokura ,  Naoto Okabe ,  Naohito Kato

发明人： Norihito Tokura ,  Naoto Okabe ,  Naohito Kato

IPC分类号： H01L29/08 ,  H01L29/739 ,  H01L29/80 ,  H01L23/58 ,  H01L29/76 ,  H01L29/861

CPC分类号： H01L29/0834 ,  H01L29/7395 ,  H01L2924/0002

摘要： An insulated gate bipolar transistor has a reverse conducting function built therein. A semiconductor layer of a first conduction type is formed on the side of a drain, a semiconductor layer of a second conduction type for causing conductivity modulation upon carrier injection is formed on the semiconductor layer of the first conduction type, a semiconductor layer of the second conduction type for taking out a reverse conducting current opposite in direction to a drain current is formed in the semiconductor layer of the second conduction type which is electrically connected to a drain electrode, and a semiconductor layer of the second conduction type is formed at or in the vicinity of a pn junction, through which carriers are given and received to cause conductivity modulation, with a high impurity concentration resulting in a path for the reverse conducting current into a pattern not impeding the passage of the carriers. Therefore, the built-in reverse conducting function has a low operating resistance, a large reverse current can be passed, there is no increase in on-resistance, and the turn-off time can be shortened.

摘要翻译： 绝缘栅双极晶体管内置有反向导通功能。 第一导电类型的半导体层形成在漏极侧，在第一导电类型的半导体层上形成用于在载流子注入时引起导电性调制的第二导电类型的半导体层，第二导电类型的半导体层 在与漏电极电连接的第二导电类型的半导体层中形成用于取出与漏电流方向相反的反向导通电流的导通型，并且在第二导电类型的半导体层中形成第二导电类型的半导体层 pn结的附近，赋予和接收载流子以引起电导率调制的pn结附近，杂质浓度高，导致反向导通电流进入不妨碍载流子通过的图案的路径。 因此，内置的反向导通功能具有低的工作电阻，可以通过大的反向电流，导通电阻不增加，并且可以缩短关断时间。

公开(公告)号：US5510634A

公开(公告)日：1996-04-23

申请号：US324508

申请日：1994-10-18

申请人： Naoto Okabe ,  Naohito Kato

发明人： Naoto Okabe ,  Naohito Kato

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/739 ,  H01L29/74 ,  H01L23/58

CPC分类号： H01L29/0626 ,  H01L29/7395 ,  H01L2924/0002

摘要： An IGBT chip includes a unit cell region and a guard ring region which surrounds the unit cell region. In the unit cell region, a plurality of IGBT unit cells are formed, each of which comprises a base layer, a source layer, a common gate electrode, a common source electrode, and a common drain electrode. In the guard ring region, at least one diffused layer making up a guard ring is formed. Further, an annular diffused layer is formed and is connected to the drain electrode. The annular diffused layer is disposed away from the outermost guard ring by a specified length. This length is such that the punch-through occurs before the avalanche breakdown voltage of the junction associated with the outermost guard ring. Therefore, the withstand voltage against the avalanche breakdown when surge voltage is applied to the drain electrode is improved.

摘要翻译： IGBT芯片包括单元区域和围绕单元区域的保护环区域。 在单元电池区域中，形成多个IGBT单位电池，每个IGBT单元电池包括基极层，源极层，公共栅电极，公共源电极和公共漏电极。 在保护环区域中，形成形成保护环的至少一个扩散层。 此外，形成环形扩散层并连接到漏电极。 环形扩散层远离最外侧保护环设置一定长度。 该长度使得穿孔发生在与最外侧保护环相关联的结的雪崩击穿电压之前。 因此，提高了当向漏电极施加浪涌电压时抵抗雪崩击穿的耐受电压。

公开(公告)号：US5475258A

公开(公告)日：1995-12-12

申请号：US405410

申请日：1995-03-15

申请人： Naohito Kato ,  Etsuji Toyoda ,  Naoto Okabe

发明人： Naohito Kato ,  Etsuji Toyoda ,  Naoto Okabe

IPC分类号： H01L21/76 ,  H01L27/02 ,  H01L27/04 ,  H01L29/78 ,  H01L29/866 ,  H01L29/161 ,  H01L29/20 ,  H01L29/22

CPC分类号： H01L29/7808 ,  H01L27/0255 ,  H01L27/0288 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7322 ,  H01L29/7395

摘要： A semiconductor device has a protective Zener diode formed through an insulation film to a silicon substrate having a power MOSFET formed thereon. The breakdown strength of the insulation film is substantially improved and the withstand voltage of the Zener diode can be set to a high value. A gate plate 11 electrically connected to an outer circumferential part of a p-type diffusion region 104 is installed, and element parts 112a-112c and equipotential plates 113a-133c constituting a Zener diode group 115 are formed. The equipotential plates 113a-133c hold a prescribed potential by Zener diode pairs 114 of the element parts 112a-112c.

摘要翻译： 半导体器件具有通过绝缘膜形成的保护齐纳二极管，该保护齐纳二极管形成在其上形成功率MOSFET的硅衬底。 绝缘膜的击穿强度显着提高，并且齐纳二极管的耐受电压可以设定为高值。 安装了与p型扩散区域104的外周部电连接的栅板11，形成构成齐纳二极管组115的元件部分112a-112c和等电位板113a-133c。 等电位板113a-133c由元件部分112a-112c的齐纳二极管对114保持规定的电位。

公开(公告)号：US06281546B1

公开(公告)日：2001-08-28

申请号：US08993405

申请日：1997-12-18

申请人： Yoshihiko Ozeki ,  Naoto Okabe ,  Naohito Kato

发明人： Yoshihiko Ozeki ,  Naoto Okabe ,  Naohito Kato

IPC分类号： H01L2976

CPC分类号： H01L29/7395 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7816

摘要： A wide high concentration P+ type region is formed on the surface of an N− type epitaxial layer formed on a P type substrate in the vicinity of the edge portion of a cell region in which a transistor device is formed. As a result, holes generated at the outside of the cell region mostly flow through the P+ type region and reach to an emitter electrode. Therefore, the flow amount of the holes does not concentrate on a channel P well for forming a channel region of the transistor device at the cell edge portion, whereby a ruggedness against a latch-up phenomenon can be improved.

摘要翻译： 在形成有晶体管器件的单元区域的边缘部分附近的P型衬底上形成的N型外延层的表面上形成宽的高浓度P +型区域。 结果，在电池区域外部产生的空穴大部分流过P +型区域并到达发射电极。 因此，孔的流量不会集中在用于在单元边缘部分形成晶体管器件的沟道区的沟道P上，从而可以提高抵抗闩锁现象的坚固性。

公开(公告)号：US5973338A

公开(公告)日：1999-10-26

申请号：US947402

申请日：1997-10-08

申请人： Naoto Okabe ,  Norihito Tokura ,  Naohito Kato

发明人： Naoto Okabe ,  Norihito Tokura ,  Naohito Kato

IPC分类号： H01L29/68 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/1095 ,  H01L29/7395

摘要： An insulated gate type bipolar-transistor (IGBT) incorporates an excess voltage protecting function and drain voltage fixing function in a monolithic structure. Impurity concentration ND and the thickness of an n.sup.- type drain layer (3) is set so that a depletion region propagating from a p type base layer (7) reaches a p.sup.+ type drain layer at a voltage (V.sub.DSP) lower than a voltage (V.sub.DSS) at which avalanche breakdown is caused within the IGBT element when voltage is applied between the source and the drain.

摘要翻译： 绝缘栅型双极晶体管（IGBT）在整体结构中包含过电压保护功能和漏极电压固定功能。 杂质浓度ND和n型漏极层（3）的厚度被设定为使得从ap型基极层（7）传播的耗尽区域在低于电压（VDSS）的VDSP下达到p +型漏极层 ），当在源极和漏极之间施加电压时，在IGBT元件内引起雪崩击穿。