公开(公告)号：US5169793A

公开(公告)日：1992-12-08

申请号：US710721

申请日：1991-06-07

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Naohito Kato

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Naohito Kato

IPC分类号： H01L21/8234 ,  H01L21/331 ,  H01L27/088 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/66333 ,  H01L29/1095

摘要： A p type pad well layer is formed at the surface of an n.sup.- type drain layer under a gate bonding pad and the surface thereof is provided with a p.sup.++ type pad layer to be provided with lower resistivity. The p.sup.++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, the introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p.sup.++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p.sup.++ type pad layer can be easily formed. The p.sup.++ type pad layer serves as a low resistance path for allowing the holes flowing into the region under the pad region of the insulated gate bipolar transistor to escape to the source electrode, whereby occurrence of the latch up and increase in the turn-off time due to the minority carriers concentrating into the border portion cell located adjacent to the pad region can be prevented.

摘要翻译： p型衬垫阱层形成在栅极焊盘下方的n型漏极层的表面处，并且其表面设置有具有较低电阻率的p ++型焊盘层。 p ++型垫层通过接触孔与源电极连接。 由于向每个单元提供栅极电位的栅极电极具有沿着焊盘区域和单元区域之间的边界布置的梳齿形式的延伸的图案，所以在焊盘下面基本上不存在栅电极。 因此，在形成栅电极之后，可以在形成p ++型接触层的同时进行在焊盘区域下方的阱层的整个表面的杂质的引入，因此，低电阻p ++型焊盘层可以容易地 形成。 p ++型衬垫层用作低电阻路径，用于允许流入绝缘栅双极晶体管的焊盘区域下方的空穴逸出到源电极，由此发生闭锁并增加关断时间 由于可以防止集中在位于焊盘区域附近的边界部分单元的少数载流子。

公开(公告)号：US6107661A

公开(公告)日：2000-08-22

申请号：US720018

申请日：1996-09-27

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/7809

摘要： A concave channel type DMOS structure having an improved gate-to-source breakdown voltage are disclosed. By establishing a curvature at a corner portion of a lattice-like pattern in a groove portion for forming the concave channel structure, the shape of the tip of a three-dimensionally projecting portion of a semiconductor region determined by a plane angle of the corner portion in the lattice-like pattern and an inclination of the groove portion is rounded. That is, a three-dimensionally sharpened corner portion in the concave channel structure is rounded, and thereby electric field concentration at the corner portion is suppressed.

摘要翻译： 公开了具有改善的栅 - 源击穿电压的凹沟道型DMOS结构。 通过在用于形成凹槽结构的凹槽部分中的格子状图案的角部处建立曲率，由角部分的平面角确定的半导体区域的三维突出部分的尖端的形状 呈格子状，槽部的倾斜为圆形。 也就是说，凹槽结构中的三维锐角部分是圆形的，从而抑制角部处的电场集中。

公开(公告)号：US5464992A

公开(公告)日：1995-11-07

申请号：US358983

申请日：1994-12-19

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Naohito Kato

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Naohito Kato

IPC分类号： H01L21/8234 ,  H01L21/331 ,  H01L27/088 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L27/01 ,  H01L33/00

CPC分类号： H01L29/66333 ,  H01L29/1095

摘要： A p type pad well layer is formed at the surface of an n.sup.- type drain layer under a gate bonding pad and the surface thereof is provided with a p.sup.++ type pad layer to be provided with lower resistivity. The p.sup.++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p.sup.++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p.sup.++ type pad layer can be easily formed. The p.sup.++ type pad layer serves as a low resistance path for allowing the holes flowing into the region under the pad region of the insulated gate bipolar transistor to escape to the source electrode, whereby occurrence of the latch up and increase in the turn-off time due to the minority carriers concentrating into the border portion cell located adjacent to the pad region can be prevented.

摘要翻译： p型衬垫阱层形成在栅极焊盘下方的n型漏极层的表面处，并且其表面设置有具有较低电阻率的p ++型焊盘层。 p ++型垫层通过接触孔与源电极连接。 由于向每个单元提供栅极电位的栅极电极具有沿着焊盘区域和单元区域之间的边界布置的梳齿形式的延伸的图案，所以在焊盘下面基本上不存在栅电极。 因此，在形成栅极电极之后，可以在形成p ++型接触层的同时进行在焊盘区域下方的阱层的整个表面的杂质的引入，因此能够容易地形成低电阻p ++型焊盘层 。 p ++型衬垫层用作低电阻路径，用于允许流入绝缘栅双极晶体管的焊盘区域下方的空穴逸出到源电极，由此发生闭锁并增加关断时间 由于可以防止集中在位于焊盘区域附近的边界部分单元的少数载流子。

公开(公告)号：US6100140A

公开(公告)日：2000-08-08

申请号：US675774

申请日：1996-07-03

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

IPC分类号： H01L21/324 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7813

摘要： A manufacturing method of a vertical type MOSFET, which can suppress vaporization of impurity from a semiconductor substrate and prevent variation in carrier density of the channel, is disclosed. The vertical type MOSFET is formed by forming a local oxide film to form a concavity on the element surface, removing the local oxide film by wet-etching technique, forming the gate oxide film at the sidewall of the concavity by thermal oxidation, and forming a gate electrode. Further, a polycrystalline silicon is formed on a back surface of the semiconductor substrate before removing the local oxide film. Accordingly, since the polycrystalline silicon is not removed when removing the local oxide film, vaporization of impurity from the semiconductor substrate is suppressed during the thermal oxidation for forming the gate oxide film, thereby preventing change in the carrier density of the channel.

摘要翻译： 公开了一种垂直型MOSFET的制造方法，其可以抑制杂质从半导体衬底蒸发并防止沟道的载流子密度的变化。 垂直型MOSFET通过形成局部氧化膜以在元件表面上形成凹陷而形成，通过湿蚀刻技术去除局部氧化膜，通过热氧化在凹部的侧壁处形成栅极氧化膜，并形成 栅电极。 此外，在去除局部氧化物膜之前，在半导体衬底的背面上形成多晶硅。 因此，由于在去除局部氧化膜时不去除多晶硅，因此在形成栅极氧化膜的热氧化期间抑制了半导体衬底的杂质蒸发，从而防止了沟道的载流子密度的变化。

公开(公告)号：US5925911A

公开(公告)日：1999-07-20

申请号：US638374

申请日：1996-04-26

申请人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

发明人： Naoto Okabe ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

IPC分类号： H01L21/322 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7397 ,  H01L21/3221 ,  H01L29/7809 ,  H01L29/7813

摘要： A semiconductor device having a concavity formed by LOCOS technique, in which defects induced due to the LOCOS oxidation step or a following heat-treatment step are suppressed, is disclosed. An n.sup.+ type region, the impurity concentration of which is caused to be 1.times.10.sup.19 cm.sup.-3 or more, is formed in an n.sup.- type semiconductor layer. By means of this, defects occur within the n.sup.+ type region or in a proximity of the boundary of the n.sup.+ type region and the n.sup.- type semiconductor layer. The defects trap contaminant impurities taken into the wafer during the manufacturing steps, and cause contaminant impurities existing in the proximity of a concavity of the semiconductor surface to be reduced. As a result thereof, defect occurrence in the proximity of the concavity can be suppressed, and occurrence of leakage and degradation in breakdown voltage between drain and source accompanying defect occurrence in a channel region can be suppressed.

摘要翻译： 公开了一种具有通过LOCOS技术形成的凹陷的半导体器件，其中抑制了由于LOCOS氧化步骤或随后的热处理步骤引起的缺陷。 在n-型半导体层中形成其杂质浓度为1×1019 cm -3以上的n +型区域。 借此，在n +型区域或n +型区域和n型半导体层的边界附近发生缺陷。 这些缺陷会在制造步骤期间捕获杂质吸收到晶片中，并且导致存在于半导体表面的凹部附近的污染物杂质减少。 结果，可以抑制在凹部附近的缺陷发生，并且可以抑制在沟道区域中伴随缺陷发生的泄漏和源极之间的击穿电压的发生和劣化。

公开(公告)号：US5753943A

公开(公告)日：1998-05-19

申请号：US612285

申请日：1996-03-07

申请人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

发明人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/322 ,  H01L21/331 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739 ,  H01L29/749

CPC分类号： H01L29/66333 ,  H01L21/3221 ,  H01L29/0834 ,  H01L29/7395 ,  Y10S257/913

摘要： In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

公开(公告)号：US6146947A

公开(公告)日：2000-11-14

申请号：US54493

申请日：1998-04-03

申请人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

发明人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/322 ,  H01L21/331 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739

CPC分类号： H01L29/66333 ,  H01L21/3221 ,  H01L29/0834 ,  H01L29/7395 ,  Y10S257/913

摘要： In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

摘要翻译： 在绝缘栅型场效应晶体管及其制造方法中，通过热扩散在氧化气氛下在半导体衬底中形成扩散区，并且通过气相在半导体衬底上形成第一导电类型半导体层 形成扩散区后的外延。 此后，半导体层的表面变平，在平坦的半导体层上形成栅极绝缘膜和栅电极。 此外，在半导体层中形成阱区以及源极区，形成绝缘栅型场效应晶体管。 由于形成绝缘栅型场效应晶体管的半导体层的表面平坦化，即使在晶片中形成嵌入区域，也可以防止栅源绝缘耐压特性劣化。

公开(公告)号：US06452219B1

公开(公告)日：2002-09-17

申请号：US08917488

申请日：1997-08-26

申请人： Yoshiyuki Miyase ,  Naohito Kato ,  Haruo Kawakita ,  Naoto Okabe

发明人： Yoshiyuki Miyase ,  Naohito Kato ,  Haruo Kawakita ,  Naoto Okabe

IPC分类号： H01L2974

CPC分类号： H01L29/66333 ,  H01L29/1095 ,  H01L29/7395 ,  Y10S257/913

摘要： An IGBT having a buffer layer for shortening the turn-off time and for preventing the latching up is improved. The buffer layer of the present invention is not bare at the edge of a diced cross-section of the IGBT chip. According to this construction, a withstanding voltage between a semiconductor substrate and the buffer layer is lower than the withstand voltage of the pn junction at the edge of the diced cross-section. Therefore, the whole pn junction between the semiconductor substrate and the buffer layer, which has wide area, breaks down, as a result, energy caused by a negative voltage is absorbed, and the withstanding voltage against the negative voltage is improved.

摘要翻译： 具有用于缩短关断时间和防止闭锁的缓冲层的IGBT得到改善。 本发明的缓冲层在IGBT芯片的切割截面的边缘处不裸露。 根据这种结构，半导体衬底和缓冲层之间的耐电压低于切割截面边缘处的pn结的耐电压。 因此，半导体衬底与具有宽面积的缓冲层之间的整个pn结被分解，结果，由负电压引起的能量被吸收，并且抵抗负电压的耐受电压提高。

公开(公告)号：US5801445A

公开(公告)日：1998-09-01

申请号：US818729

申请日：1997-03-14

申请人： Yasuo Ishihara ,  Haruo Kawakita ,  Naoto Okabe

发明人： Yasuo Ishihara ,  Haruo Kawakita ,  Naoto Okabe

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/607 ,  H01L29/45 ,  H01L29/78 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/76

CPC分类号： H01L29/456 ,  H01L21/28512 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/85 ,  H01L29/7813 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05073 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/45124 ,  H01L2224/4847 ,  H01L2224/48724 ,  H01L2224/85205 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/05042 ,  H01L2924/12036 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/2076

摘要： A semiconductor device has an electrode interposed between an interlayer insulation film and a wire which is bonded thereto. A main component of the electrode is aluminum and the electrode contains fine-grained silicon in a concentration of 0.1 to 0.6 weight %. As a result, even if large ultrasonic power, a large load or the like is applied to the electrode when the wire is wire-bonded, damage such as the formation of a crack hardly generates at the interlayer insulation film. Therefore, the occurrence of defects due to the wire-bonding can be reduced.

摘要翻译： 半导体器件具有介于层间绝缘膜和与其结合的导线之间的电极。 电极的主要成分是铝，电极含有浓度为0.1〜0.6重量％的细晶硅。 结果，即使在线材接合时，即使大的超声波功率，大的负载等被施加到电极，在层间绝缘膜处几乎不产生诸如形成裂纹的损伤。 因此，可以减少由于引线接合引起的缺陷的发生。

公开(公告)号：US5723882A

公开(公告)日：1998-03-03

申请号：US401506

申请日：1995-03-10

申请人： Naoto Okabe ,  Naohito Kato

发明人： Naoto Okabe ,  Naohito Kato

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L29/76 ,  H01L23/58

CPC分类号： H01L29/7802 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/7395 ,  H01L29/0619 ,  H01L2924/0002

摘要： An insulated gate field effect transistor comprising a semiconductor substrate having one side on which a cell area is composed of a plurality of first wells of a first conductivity type, each of the first wells containing a source region of a second conductivity type. A channel region is defined in the surface portion of the semiconductor substrate adjoining to the source region, and a gate electrode is formed, via a gate insulating film, at least over the channel region. A source electrode is in common contact with the respective source regions of the plurality of first wells. The semiconductor substrate has a drain electrode provided on another side. A current flows between the source electrode and the drain electrode through the channel being controlled by a voltage applied to the gate electrode. A guard ring area is disposed on the one side of the semiconductor substrate so as to surround the cell area. The source electrode has an extension connected to a second well of a second conductivity type formed in the one side between the cell area and the guard ring area to provide a by-pass such that, when a current concentration occurs within the guard ring area, the concentrated current is conducted directly to the source electrode in the cell area through the by-pass, thereby preventing the concentrated current from causing a forward biassing between the first wells and the source region.

摘要翻译： 一种绝缘栅场效应晶体管，包括半导体衬底，所述半导体衬底具有一个单元面积由多个第一导电类型的第一阱组成的第一阱，每个第一阱包含第二导电类型的源极区。 在与源极区域相邻的半导体衬底的表面部分中限定沟道区，并且通过栅极绝缘膜至少在沟道区上形成栅电极。 源电极与多个第一阱的各个源极区共同接触。 半导体衬底具有设置在另一侧的漏电极。 A电流通过通过施加到栅电极的电压控制的沟道在源电极和漏电极之间流动。 保护环区域设置在半导体衬底的一侧，以围绕电池区域。 源电极具有连接到形成在电池区域和保护环区域之间的一侧中的第二导电类型的第二阱的延伸部，以提供旁路，使得当在保护环区域内发生电流集中时， 集中电流通过旁路直接传导到电池区域中的源电极，从而防止集中电流在第一阱和源极区域之间引起正向偏压。