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    Semiconductor device and method for forming the same
    1.
    发明授权
    Semiconductor device and method for forming the same 有权
    半导体装置及其形成方法

    公开(公告)号：US08183633B2

    公开(公告)日：2012-05-22

    申请号：US12847974

    申请日：2010-07-30

    Applicant: O-Kyun Kwon ,  Dong-Woo Suh ,  Jung-Hyung Pyo ,  Gyung-Ock Kim

    Inventor： O-Kyun Kwon ,  Dong-Woo Suh ,  Jung-Hyung Pyo ,  Gyung-Ock Kim

    IPC: H01L27/12

    CPC classification number: H01L21/76267 ,  H01L21/76283

    Abstract: Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one direction from the substrate is formed on the buried insulating layer. A first insulating layer is formed to enclose the silicon pattern.

    Abstract translation: 提供半导体及其形成方法。 该方法包括在衬底中局部形成掩埋绝缘层。 蚀刻衬底以形成露出掩埋绝缘层的开口，并且在掩埋绝缘层上形成从衬底至少一个方向间隔开的硅图案。 形成第一绝缘层以包围硅图案。

    Semiconductor device and method for forming the same
    2.
    发明授权
    Semiconductor device and method for forming the same 有权
    半导体装置及其形成方法

    公开(公告)号：US07790567B2

    公开(公告)日：2010-09-07

    申请号：US12130877

    申请日：2008-05-30

    Applicant: O-Kyun Kwon ,  Dong-Woo Suh ,  Jung-Hyung Pyo ,  Gyung-Ock Kim

    Inventor： O-Kyun Kwon ,  Dong-Woo Suh ,  Jung-Hyung Pyo ,  Gyung-Ock Kim

    IPC: H01L21/76

    CPC classification number: H01L21/76267 ,  H01L21/76283

    Abstract: Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one direction from the substrate is formed on the buried insulating layer. A first insulating layer is formed to enclose the silicon pattern.

    Abstract translation: 提供半导体及其形成方法。 该方法包括在衬底中局部形成掩埋绝缘层。 蚀刻衬底以形成露出掩埋绝缘层的开口，并且在掩埋绝缘层上形成从衬底至少一个方向间隔开的硅图案。 形成第一绝缘层以包围硅图案。

    Semiconductor integrated circuits including grating coupler for optical communication and methods of forming the same
    3.
    发明授权
    Semiconductor integrated circuits including grating coupler for optical communication and methods of forming the same 有权
    包括用于光通信的光栅耦合器的半导体集成电路及其形成方法

    公开(公告)号：US08165437B2

    公开(公告)日：2012-04-24

    申请号：US12684677

    申请日：2010-01-08

    Applicant: Jung-Hyung Pyo ,  O-Kyun Kwon ,  Gyung-Ock Kim

    Inventor： Jung-Hyung Pyo ,  O-Kyun Kwon ,  Gyung-Ock Kim

    IPC: G02B6/34 ,  G02B6/42

    CPC classification number: G02B6/34 ,  G02B6/124 ,  G02B6/30

    Abstract: Provided are semiconductor integrated circuits including a grating coupler for optical communication and methods of forming the same. The semiconductor integrated circuit includes: a cladding layer disposed on a semiconductor substrate; a grating coupler including an optical waveguide on the cladding layer and a grating on the optical waveguide; and at least one reflector formed in the cladding layer below the grating.

    Abstract translation: 提供了包括用于光通信的光栅耦合器的半导体集成电路及其形成方法。 半导体集成电路包括：设置在半导体衬底上的覆层; 包括在所述包层上的光波导的光栅耦合器和所述光波导上的光栅; 以及形成在光栅下方的包覆层中的至少一个反射器。

    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
    半导体器件及其形成方法

    公开(公告)号：US20100301448A1

    公开(公告)日：2010-12-02

    申请号：US12847974

    申请日：2010-07-30

    Applicant: O-Kyun KWON ,  Dong-Woo Suh ,  Junghyung Pyo ,  Gyung-Ock Kim

    Inventor： O-Kyun KWON ,  Dong-Woo Suh ,  Junghyung Pyo ,  Gyung-Ock Kim

    IPC: H01L27/12

    CPC classification number: H01L21/76267 ,  H01L21/76283

    Abstract: Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one direction from the substrate is formed on the buried insulating layer. A first insulating layer is formed to enclose the silicon pattern.

    Abstract translation: 提供半导体及其形成方法。 该方法包括在衬底中局部形成掩埋绝缘层。 蚀刻衬底以形成露出掩埋绝缘层的开口，并且在掩埋绝缘层上形成从衬底至少一个方向间隔开的硅图案。 形成第一绝缘层以包围硅图案。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20100159674A1

    公开(公告)日：2010-06-24

    申请号：US12488577

    申请日：2009-06-21

    Applicant: In-Gyoo Kim ,  O-Kyun Kwon ,  Dong-Woo Suh ,  Gyung-Ock Kim

    Inventor： In-Gyoo Kim ,  O-Kyun Kwon ,  Dong-Woo Suh ,  Gyung-Ock Kim

    IPC: H01L21/20

    CPC classification number: H01L21/2007 ,  H01L21/76251

    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a first layer, a second layer, an ion implantation layer between the first and second layers, and an anti-oxidation layer on the second layer, and performing a heat treating process to form an insulating layer between the first and second layers while preventing loss of the second layer using the anti-oxidation layer.

    Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在第一层和第二层之间形成第一层，第二层，离子注入层和第二层上的抗氧化层，并进行热处理工艺，以在第一层和第二层之间形成绝缘层 同时防止使用抗氧化层损失第二层。

    Method of fabricating semiconductor device
    6.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07927988B2

    公开(公告)日：2011-04-19

    申请号：US12488577

    申请日：2009-06-21

    Applicant: In-Gyoo Kim ,  O-Kyun Kwon ,  Dong-Woo Suh ,  Gyung-Ock Kim

    Inventor： In-Gyoo Kim ,  O-Kyun Kwon ,  Dong-Woo Suh ,  Gyung-Ock Kim

    IPC: H01L21/425

    CPC classification number: H01L21/2007 ,  H01L21/76251

    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a first layer, a second layer, an ion implantation layer between the first and second layers, and an anti-oxidation layer on the second layer, and performing a heat treating process to form an insulating layer between the first and second layers while preventing loss of the second layer using the anti-oxidation layer.

    Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在第一层和第二层之间形成第一层，第二层，离子注入层和第二层上的抗氧化层，并进行热处理工艺以在第一层和第二层之间形成绝缘层 同时防止使用抗氧化层损失第二层。

    PHOTONICS DEVICE HAVING ARRAYED WAVEGUIDE GRATING STRUCTURES
    7.
    发明申请
    PHOTONICS DEVICE HAVING ARRAYED WAVEGUIDE GRATING STRUCTURES 审中-公开
    具有阵列波导光栅结构的光电器件

    公开(公告)号：US20100150499A1

    公开(公告)日：2010-06-17

    申请号：US12477907

    申请日：2009-06-04

    Applicant: Duk-Jun Kim ,  Jung-Hyung Pyo ,  Jung-Ho Song ,  In-Gyoo Kim ,  Gyung-Ock Kim

    Inventor： Duk-Jun Kim ,  Jung-Hyung Pyo ,  Jung-Ho Song ,  In-Gyoo Kim ,  Gyung-Ock Kim

    IPC: G02B6/34 ,  G02B6/26

    CPC classification number: G02B6/12011

    Abstract: Provided is a photonics device including at least two arrayed waveguide grating structures. Each of the arrayed waveguide grating structures of the photonics device includes an input star coupler, an output star coupler, and a plurality of arrayed waveguides optically connecting the input star coupler to the output star coupler. Each of the arrayed waveguides includes at least one first section having a high confinement factor and at least two second sections having a low confinement factor. The first sections of the arrayed waveguides have the same structure.

    Abstract translation: 提供了包括至少两个阵列波导光栅结构的光子器件。 光子器件的每个阵列波导光栅结构包括输入星形耦合器，输出星形耦合器和将输入星形耦合器光耦合到输出星形耦合器的多个阵列波导。 每个阵列波导包括具有高约束因子的至少一个第一部分和具有低约束因子的至少两个第二部分。 阵列波导的第一部分具有相同的结构。

    Waveguide structure
    8.
    发明授权
    Waveguide structure 失效
    波导结构

    公开(公告)号：US07693384B2

    公开(公告)日：2010-04-06

    申请号：US12111884

    申请日：2008-04-29

    Applicant: Jong-Moo Lee ,  Duk-Jun Kim ,  O-Kyun Kwon ,  Gyung-Ock Kim

    Inventor： Jong-Moo Lee ,  Duk-Jun Kim ,  O-Kyun Kwon ,  Gyung-Ock Kim

    IPC: G02B6/10

    CPC classification number: G02B6/12007

    Abstract: A waveguide structure is provided. The waveguide structure includes: a slot channel waveguide including first and second patterns, which are spaced apart from each other to define a slot; a first upper layer covering at least a portion of the slot channel waveguide; and a second upper layer covering the remaining portion of the slot channel waveguide. A thermo-optic coefficient (TOC) of the channel waveguide times a TOC of the second upper layer is a negative number.

    Abstract translation: 提供了一种波导结构。 波导结构包括：缝隙通道波导，包括第一和第二图案，它们彼此间隔开以限定狭槽; 覆盖所述槽道波导的至少一部分的第一上层; 以及覆盖槽道波导的剩余部分的第二上层。 通道波导的热光系数（TOC）乘以第二上层的TOC是负数。

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