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    Configuration for determining a concentration of contaminating particles in a loading and unloading chamber of an appliance for processing at least one disk-like object
    1.
    发明授权
    Configuration for determining a concentration of contaminating particles in a loading and unloading chamber of an appliance for processing at least one disk-like object 失效
    用于确定用于处理至少一个盘状物体的器具的装载和卸载室中的污染颗粒浓度的配置

    公开(公告)号：US06928892B2

    公开(公告)日：2005-08-16

    申请号：US10233901

    申请日：2002-09-03

    申请人： Olaf Storbeck ,  Ralph Trunk ,  Lothar Pfitzner ,  Claus Schneider

    发明人： Olaf Storbeck ,  Ralph Trunk ,  Lothar Pfitzner ,  Claus Schneider

    IPC分类号： G01N15/06

    CPC分类号： G01N15/06

    摘要： A configuration for measuring the concentration of contaminating particles at high time resolution in the mini environments of loading and unloading chambers of processing appliances in semiconductor fabrication includes a probe, a movement unit for the probe, a particle detector, vacuum pump and a control unit. Reaching critical layer thicknesses of disk carriers or boats in ovens, and maladjustments of handling systems for wafers, masks, flat panel displays and other disc-like objects can be detected in terms of the cause and quantified immediately. The movement unit moves the probe to a desired position in the loading and unloading chamber as a reaction to the positioning of the handling system. A method of operating the configuration is also provided.

    摘要翻译： 用于在半导体制造中的加工装置的装卸室的微型环境中以高时间分辨率测量污染粒子的浓度的结构包括探针，用于探针的移动单元，粒子检测器，真空泵和控制单元。 达到在烤箱中的盘式载体或船的关键层厚度，以及对于晶片，掩模，平板显示器和其它盘状物体的处理系统的调整可以根据原因被检测并立即量化。 移动单元将探针移动到装载和卸载室中的期望位置，作为对处理系统的定位的反应。 还提供了一种操作该配置的方法。

    Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates
    2.
    发明申请
    Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates 失效
    沟槽电容器结构和用于在半导体衬底中施加用于沟槽蚀刻工艺的覆盖层和掩模的工艺

    公开(公告)号：US20050118777A1

    公开(公告)日：2005-06-02

    申请号：US10974797

    申请日：2004-10-28

    申请人： Henry Bernhardt ,  Michael Stadtmuller ,  Olaf Storbeck ,  Stefan Kainz

    发明人： Henry Bernhardt ,  Michael Stadtmuller ,  Olaf Storbeck ,  Stefan Kainz

    IPC分类号： H01L21/20 ,  H01L21/308 ,  H01L21/31 ,  H01L21/314 ,  H01L21/318 ,  H01L21/334 ,  H01L21/469 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10861 ,  H01L21/3081 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/1087 ,  H01L29/66181

    摘要： A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer. The thermal nitriding is advantageously incorporated into a preanneal step for expelling oxygen from the semiconductor substrate, so that the semiconductor substrate is protected from the etching action of the expelled oxygen by the stress relief layer which is formed, there is no need for an additional temporary etching protection layer for the semiconductor substrate and the overall processing is streamlined.

    摘要翻译： 单晶半导体衬底和沉积的氮化硅层或衬垫氮化物之间的应力消除层由热生产的氮化硅形成。 由热产生的氮化硅制成的应力消除层代替例如与掩模层结合在该位置上通常的二氧化硅层或焊盘氧化物。 在包括由沉积的氮化硅形成的保护层部分的掩模图案化之后，根据本发明为应力消除层提供的材料减少了对随后的工艺步骤施加的限制，例如湿蚀刻步骤， 在半导体衬底或半导体衬底中的结构以及应力消除层上均起作用。 热氮化有利地结合到用于从半导体衬底排出氧的预退火步骤中，使得半导体衬底被形成的应力消除层免受排出的氧的蚀刻作用，不需要额外的临时 用于半导体衬底的蚀刻保护层和整体处理被简化。

    Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates
    5.
    发明授权
    Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates 失效
    沟槽电容器结构和用于在半导体衬底中施加用于沟槽蚀刻工艺的覆盖层和掩模的工艺

    公开(公告)号：US07547646B2

    公开(公告)日：2009-06-16

    申请号：US10974797

    申请日：2004-10-28

    申请人： Henry Bernhardt ,  Michael Stadtmüller ,  Olaf Storbeck ,  Stefan Kainz

    发明人： Henry Bernhardt ,  Michael Stadtmüller ,  Olaf Storbeck ,  Stefan Kainz

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L27/10861 ,  H01L21/3081 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/1087 ,  H01L29/66181

    摘要： A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer. The thermal nitriding is advantageously incorporated into a preanneal step for expelling oxygen from the semiconductor substrate, so that the semiconductor substrate is protected from the etching action of the expelled oxygen by the stress relief layer which is formed, there is no need for an additional temporary etching protection layer for the semiconductor substrate and the overall processing is streamlined.

    摘要翻译： 单晶半导体衬底和沉积的氮化硅层或衬垫氮化物之间的应力消除层由热生产的氮化硅形成。 由热产生的氮化硅制成的应力消除层代替例如与掩模层结合在该位置上通常的二氧化硅层或焊盘氧化物。 在包括由沉积的氮化硅形成的保护层部分的掩模图案化之后，根据本发明为应力消除层提供的材料减少了对随后的工艺步骤施加的限制，例如湿蚀刻步骤， 在半导体衬底或半导体衬底中的结构以及应力消除层上均起作用。 热氮化有利地结合到用于从半导体衬底排出氧的预退火步骤中，使得半导体衬底被形成的应力消除层免受排出的氧的蚀刻作用，不需要额外的临时 用于半导体衬底的蚀刻保护层和整体处理被简化。