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    ACCESSING INDEPENDENTLY ADDRESSABLE MEMORY CHIPS
    2.
    发明申请
    ACCESSING INDEPENDENTLY ADDRESSABLE MEMORY CHIPS 审中-公开
    访问独立的可访问记忆卡

    公开(公告)号：US20150071021A1

    公开(公告)日：2015-03-12

    申请号：US14024201

    申请日：2013-09-11

    申请人： Oracle International Corporation

    发明人： Philip Amberg ,  Alex Chow ,  Robert David Hopkins, II

    IPC分类号： G11C11/4063

    CPC分类号： G11C8/12 ,  G06F12/0207 ,  G06F12/0607 ,  G11C2029/0411

    摘要： A method of accessing rows and columns stored in a memory system that include memory chips that can be individually addressed and accessed is described. In order to leverage this capability, prior to performing a row-write request on the memory system, a computer system may transform the rows and the columns in a matrix. In particular, in response to receiving a row-write request to write to a row N in the matrix, the computer system rotates the row right by N elements, and writes the row in parallel to address N of the memory chips in the memory system. Similarly, in response to receiving a column-write request to write to column M in the matrix, the computer system rotates the column right by M elements, and writes the column in parallel to the memory chips in the memory system.

    摘要翻译： 描述访问存储在存储器系统中的行和列的方法，该存储器系统包括可被单独寻址和访问的存储器芯片。 为了利用这种能力，在对存储器系统执行行写入请求之前，计算机系统可以以矩阵的形式转换行和列。 特别地，响应于接收到写入矩阵中的行N的行写入请求，计算机系统向右旋转N个元素，并且将行与存储器系统中的存储器芯片的地址N并行写入 。 类似地，响应于接收到写入矩阵中的列M的列写请求，计算机系统向右旋转列M M个元素，并将列并行地写入存储器系统中的存储器芯片。

    CONFIGURABLE-WIDTH MEMORY CHANNELS FOR STACKED MEMORY STRUCTURES
    5.
    发明申请
    CONFIGURABLE-WIDTH MEMORY CHANNELS FOR STACKED MEMORY STRUCTURES 有权
    用于堆叠存储器结构的可配置宽度存储器通道

    公开(公告)号：US20140185352A1

    公开(公告)日：2014-07-03

    申请号：US13732972

    申请日：2013-01-02

    申请人： ORACLE INTERNATIONAL CORPORATION

    发明人： Alex Chow ,  Philip Amberg ,  Robert David Hopkins, II

    IPC分类号： G11C5/06

    CPC分类号： G11C5/06 ,  G11C5/025 ,  G11C7/10 ,  G11C7/18 ,  G11C8/12 ,  G11C11/408

    摘要： The disclosed embodiments provide a chip package that facilitates configurable-width memory channels. In this chip package, a semiconductor die is electrically connected to two or more memory chips. More specifically, contacts on each individual memory chip are each directly connected to a distinct set of contacts on the semiconductor die such that the semiconductor die has separate, unique command and address buses to individually address and communicate with each individual memory chip. Individually addressable memory chips that are each accessed via separate command and address buses facilitate a configurable-width memory channel that efficiently supports different data-access granularities.

    摘要翻译： 所公开的实施例提供了促进可配置宽度存储器通道的芯片封装。 在该芯片封装中，半导体管芯与两个以上的存储器芯片电连接。 更具体地，每个单独存储器芯片上的触点各自直接连接到半导体管芯上的不同的触点集合，使得半导体管芯具有单独的唯一命令和地址总线，以单独地寻址并与每个单独的存储器芯片通信。 通过单独的命令和地址总线访问的可单独寻址的存储器芯片便于有效支持不同数据访问粒度的可配置宽度的存储器通道。

    OFFSET CANCELLATION FOR DC ISOLATED NODES
    6.
    发明申请
    OFFSET CANCELLATION FOR DC ISOLATED NODES 有权
    DC隔离节点偏移消除

    公开(公告)号：US20140099892A1

    公开(公告)日：2014-04-10

    申请号：US14101015

    申请日：2013-12-09

    申请人： Oracle International Corporation

    发明人： Justin M. Schauer ,  Robert David Hopkins, II ,  Robert J. Drost

    IPC分类号： H03F3/45 ,  H04B5/00

    CPC分类号： H03F3/45179 ,  H03F1/0261 ,  H03F3/45475 ,  H03F3/45973 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/54 ,  H03F2200/541 ,  H03F2203/45101 ,  H03F2203/45212 ,  H03F2203/45518 ,  H03F2203/45524 ,  H03F2203/45528 ,  H04B5/0031

    摘要： Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.

    摘要翻译： 在与输入到放大器的数据信号直流隔离的高性能放大器的输入上开发的浮动电压上的偏移电压通过在输入节点和预定电位之间连接高电阻元件而被消除，在邻近通信系统中特别有用，其中两个 芯片通过在两个芯片中共同形成的电容或电感耦合电路连接。 电阻元件可以是连接在节点和期望偏置电压之间的截止MOS晶体管，或者其栅极和漏极连接到电位的MOS晶体管。 可以将多个偏置电压分配给所有接收器，并由多路复用器本地选择以应用于接收器的一个或两个输入节点。 当电阻元件与数据速率相比具有长时间常数或电阻元件是非线性时，接收器输出也可以用作预定电位。

    Configurable-width memory channels for stacked memory structures
    8.
    发明授权
    Configurable-width memory channels for stacked memory structures 有权
    堆叠内存结构的可配置宽度内存通道

    公开(公告)号：US08917571B2

    公开(公告)日：2014-12-23

    申请号：US13732972

    申请日：2013-01-02

    申请人： Oracle International Corporation

    发明人： Alex Chow ,  Philip Amberg ,  Robert David Hopkins, II

    IPC分类号： G11C8/12 ,  G11C5/06 ,  G11C7/18 ,  G11C7/10 ,  G11C5/02

    CPC分类号： G11C5/06 ,  G11C5/025 ,  G11C7/10 ,  G11C7/18 ,  G11C8/12 ,  G11C11/408

    摘要： The disclosed embodiments provide a chip package that facilitates configurable-width memory channels. In this chip package, a semiconductor die is electrically connected to two or more memory chips. More specifically, contacts on each individual memory chip are each directly connected to a distinct set of contacts on the semiconductor die such that the semiconductor die has separate, unique command and address buses to individually address and communicate with each individual memory chip. Individually addressable memory chips that are each accessed via separate command and address buses facilitate a configurable-width memory channel that efficiently supports different data-access granularities.

    摘要翻译： 所公开的实施例提供了促进可配置宽度存储器通道的芯片封装。 在该芯片封装中，半导体管芯与两个以上的存储器芯片电连接。 更具体地，每个单独存储器芯片上的触点各自直接连接到半导体管芯上的不同的触点集合，使得半导体管芯具有单独的唯一命令和地址总线，以单独地寻址并与每个单独的存储器芯片通信。 通过单独的命令和地址总线访问的可单独寻址的存储器芯片便于有效支持不同数据访问粒度的可配置宽度的存储器通道。