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公开(公告)号:US09159861B2
公开(公告)日:2015-10-13
申请号:US14059288
申请日:2013-10-21
摘要: During a fabrication technique, trenches are defined partially through the thickness of a substrate. Then, photonic integrated circuits are coupled to the substrate. These photonic integrated circuits may be in a diving-board configuration, so that they at least partially overlap the trenches. While this may preclude the use of existing dicing techniques, individual hybrid integrated photonic chips (which each include a portion of the substrate and at least one of the photonic integrated circuits) may be singulated from the substrate by: coupling a carrier to a front surface of the substrate; thinning the substrate from a back surface until the partial trenches are reached (for example, by grinding the substrate); attaching a support mechanism (such as tape) to the back surface of the substrate; removing the carrier; and then removing the support mechanism.
摘要翻译: 在制造技术期间,通过衬底的厚度部分限定沟槽。 然后,光子集成电路耦合到衬底。 这些光子集成电路可以处于潜水板配置中,使得它们至少部分地与沟槽重叠。 虽然这可能排除了使用现有的切割技术,但是可以通过以下方式将单个混合集成光子芯片(其中每个包括基板的一部分和至少一个光子集成电路)分离成:将载体耦合到前表面 的基底; 从背面稀释基板直到达到部分沟槽(例如,通过研磨基板); 将支撑机构(例如胶带)附接到基板的背面; 移除载体; 然后卸下支撑机构。
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公开(公告)号:US20150171040A1
公开(公告)日:2015-06-18
申请号:US14109616
申请日:2013-12-17
IPC分类号: H01L23/00
CPC分类号: H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/03831 , H01L2224/03912 , H01L2224/0401 , H01L2224/05023 , H01L2224/05144 , H01L2224/05155 , H01L2224/05568 , H01L2224/05644 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13023 , H01L2224/1308 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16148 , H01L2224/16238 , H01L2224/16501 , H01L2224/16502 , H01L2224/16503 , H01L2224/81193 , H01L2224/8181 , H01L2224/81815 , H01L2924/381 , H01L2924/00014 , H01L2924/00012
摘要: This chip package includes a substrate having a multilayer electroplated stack disposed on a surface of the substrate. The multilayer electroplated stack may include one or more instances of alternating layers of gold and tin, where relative thicknesses of the alternating layers, when melted, result in a chemical composition having an initial melting temperature to form a bump and a subsequent melting temperature to reflow the bump that is higher than the initial melting temperature. For example, the chemical composition may correspond to a non-equilibrium gold-tin alloy.
摘要翻译: 该芯片封装包括具有设置在基板的表面上的多层电镀堆叠的基板。 多层电镀堆叠可以包括金和锡的交替层的一个或多个实例,其中交替层的相对厚度在熔化时导致化学组成具有初始熔融温度以形成凸块和随后的熔融温度以回流 该凸起高于初始熔化温度。 例如,化学组成可以对应于非平衡金 - 锡合金。
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公开(公告)号:US08896112B2
公开(公告)日:2014-11-25
申请号:US13838602
申请日:2013-03-15
CPC分类号: H01L24/14 , B23K3/0623 , H01L21/561 , H01L21/6836 , H01L23/296 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/74 , H01L24/81 , H01L24/98 , H01L25/0657 , H01L2221/68327 , H01L2221/68381 , H01L2224/03452 , H01L2224/0361 , H01L2224/0362 , H01L2224/0401 , H01L2224/05557 , H01L2224/05558 , H01L2224/05571 , H01L2224/05573 , H01L2224/05686 , H01L2224/11005 , H01L2224/11013 , H01L2224/11015 , H01L2224/11334 , H01L2224/13099 , H01L2224/13561 , H01L2224/1357 , H01L2224/13644 , H01L2224/13686 , H01L2224/17517 , H01L2224/742 , H01L2224/81002 , H01L2224/81141 , H01L2224/81191 , H01L2224/81815 , H01L2224/94 , H01L2924/00014 , H01L2924/05432 , H01L2224/11 , H01L2224/03 , H01L2924/00012 , H01L2924/05442 , H01L2224/05552
摘要: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. The positive features may be self-populated into the negative features on at least one of the substrates using a hydrophilic layer in the negative feature. This hydrophilic layer may be used in conjunction with a hydrophobic layer surrounding the negative features on a top surface of at least one of the substrates.
摘要翻译: 描述了多芯片模块(MCM)。 该MCM包括至少两个基板,其通过在基板的相对表面上的正和负特征机械耦合和对准。 这些积极和消极的特征可以彼此交配和自锁。 可以使用负特征中的亲水层,在至少一个基板上将负面特征自身填充到负极特征中。 该亲水层可以与围绕至少一个基底的顶表面上的负特征的疏水层结合使用。
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公开(公告)号:US20140321804A1
公开(公告)日:2014-10-30
申请号:US14047978
申请日:2013-10-07
发明人: Hiren D. Thacker , Ashok V. Krishnamoorthy , Robert David Hopkins, II , Jon Lexau , Xuezhe Zheng , Ronald Ho , Ivan Shubin , John E. Cunningham
IPC分类号: G02B6/12
CPC分类号: G02B6/4274 , H01L23/49827 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/72 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0652 , H01L25/0655 , H01L2224/0401 , H01L2224/13147 , H01L2224/1403 , H01L2224/141 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/32225 , H01L2224/72 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81815 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2225/06534 , H01L2225/06589 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/37001 , H05K3/36 , H05K2201/10484 , H01L2924/00
摘要: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are proximate to each other in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a top surface of an interposer, and this top surface is in turn electrically coupled to a front surface of an input/output (I/O) integrated circuit that faces the top surface. Furthermore, the front surface of the I/O integrated circuit is electrically coupled to a top surface of the optical integrated circuit, where the top surface of the optical integrated circuit faces the front surface of the I/O integrated circuit.
摘要翻译: 芯片封装包括在芯片封装中彼此靠近的光学集成电路(例如混合集成电路)和集成电路。 集成电路包括诸如存储器或处理器的电路,并且光学集成电路传送具有非常高带宽的光信号。 此外,集成电路的前表面电耦合到插入件的顶表面,并且该顶表面又电耦合到面向顶表面的输入/输出(I / O)集成电路的前表面 。 此外,I / O集成电路的前表面电耦合到光集成电路的顶表面,其中光集成电路的顶表面面向I / O集成电路的前表面。
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公开(公告)号:US20140270784A1
公开(公告)日:2014-09-18
申请号:US13831519
申请日:2013-03-14
CPC分类号: G02B6/4284 , G02B6/4279 , G02B6/43 , H04B10/27 , H04B10/801
摘要: An interconnect module for communicating electrical signals and optical signals is described. In particular, an integrated circuit in the interconnect module receives and transmits the electrical signals with other components in a system that includes the interconnect module via an electrical connector. In addition, the integrated circuit receives and transmits electrical signals to a hybrid silicon-photonic bridge chip that performs electrical-to-optical and optical-to-electrical conversion. In turn, this bridge chip receives and transmits optical signals via an optical fiber. The interconnect module can be remateably connected to a backplane in the system, and can be arranged in a stacked configuration with other instances of the interconnect module. In these ways, the interconnect module facilitates dense, modular or scalable, and compact electrical and optical communication in the system.
摘要翻译: 描述了用于传送电信号和光信号的互连模块。 特别地,互连模块中的集成电路经由电连接器接收并传输包括互连模块的系统中的其它部件的电信号。 此外,集成电路接收并发送电信号到执行电 - 光和光 - 电转换的混合硅 - 光子桥芯片。 反过来,该桥芯片经由光纤接收和发送光信号。 互连模块可以可重新连接到系统中的背板,并且可以以互连模块的其他实例布置成堆叠配置。 以这些方式,互连模块便于在系统中进行密集,模块化或可缩放的电气和光通信。
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公开(公告)号:US20140225284A1
公开(公告)日:2014-08-14
申请号:US13764622
申请日:2013-02-11
CPC分类号: H01L23/10 , H01L21/561 , H01L21/563 , H01L21/565 , H01L23/3128 , H01L25/0657 , H01L2224/16225 , H01L2225/06517 , H01L2225/06527 , H01L2225/06555 , H01L2225/06575 , H01L2225/06582
摘要: A chip package is described. This chip package includes a housing having a surface and a cavity, defined by an edge in the surface, with slots arranged at an angle relative to the surface. For example, the angle may be between 0° (in a plane of the surface) and 90° (perpendicular to the plane). Alternatively, the angle may be 0°. Moreover, the slots may be configured to accommodate a set of semiconductor dies arranged in a stack along a direction perpendicular to a plane of the slots, and the semiconductor dies may be offset from each other in a horizontal direction in the plane of slots so that one side of the stack defines a stepped terrace.
摘要翻译: 描述了芯片封装。 该芯片封装包括具有由表面中的边缘限定的表面和空腔的壳体,其中相对于表面以一定角度布置。 例如,角度可以在0°(表面的平面)和90°(垂直于平面)之间。 或者,该角度可以是0°。 此外,槽可以被配置为容纳沿着垂直于槽的平面的方向布置在堆叠中的一组半导体管芯,并且半导体管芯可以在槽的平面中在水平方向上彼此偏移,使得 堆叠的一侧限定了阶梯式露台。
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公开(公告)号:US20160216445A1
公开(公告)日:2016-07-28
申请号:US14605650
申请日:2015-01-26
CPC分类号: G02B6/12004 , G02B6/30 , G02B6/32 , G02B6/4219 , G02B6/4257 , G02B6/4274 , G02B2006/12061 , G02B2006/12142 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L25/167 , H01L2224/16225 , H01L2924/0002 , H01L2924/15311 , H04B10/803 , H01L2924/00
摘要: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are proximate to each other in the chip package. The integrated circuit includes electrical circuits that modulate data, communicate data, and serialize/deserialize data, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a top surface of an interposer, and a top surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit. Furthermore, a bottom surface of the optical integrated circuit faces the top surface of the interposer, and the front surface of the optical integrated circuit is optically coupled to an optical-fiber receptacle, which in turn is optically coupled to an optical-fiber connector.
摘要翻译: 芯片封装包括在芯片封装中彼此靠近的光学集成电路(例如混合集成电路)和集成电路。 该集成电路包括调制数据,传送数据和串行化/反序列化数据的电路,并且光学集成电路以非常高的带宽传送光信号。 此外,集成电路的前表面电耦合到插入件的顶表面,并且集成电路的顶表面电耦合到光学集成电路的前表面。 此外,光学集成电路的底表面面向插入件的顶表面,并且光学集成电路的前表面光学耦合到光纤插座,光纤插座又与光纤连接器光耦合。
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公开(公告)号:US09250403B2
公开(公告)日:2016-02-02
申请号:US14047910
申请日:2013-10-07
发明人: Hiren D. Thacker , Frankie Y. Liu , Robert David Hopkins, II , Jon Lexau , Xuezhe Zheng , Guoliang Li , Ivan Shubin , Ronald Ho , John E. Cunningham , Ashok V. Krishnamoorthy
IPC分类号: G02B6/12 , G02B6/42 , H01L25/065 , H01L23/00 , H05K3/36
CPC分类号: G02B6/4274 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/72 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0652 , H01L25/0655 , H01L2224/0401 , H01L2224/13147 , H01L2224/1403 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/72 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81815 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2225/06534 , H01L2225/06589 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/37001 , H05K3/36 , H05K2201/10484 , H01L2924/00
摘要: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit by a top surface of the interposer, where the top surface faces the front surface of the integrated circuit and the front surface of the optical integrated circuit. Furthermore, the integrated circuit and the optical integrated circuit may be on a same side of the interposer. By integrating the optical integrated circuit and the integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.
摘要翻译: 芯片封装包括与芯片封装中的每一个相邻的光学集成电路(例如混合集成电路)和集成电路。 集成电路包括诸如存储器或处理器的电路,并且光学集成电路传送具有非常高带宽的光信号。 此外,集成电路的前表面通过插入件的顶表面电耦合到光集成电路的前表面,其中顶表面面向集成电路的前表面和光集成电路的前表面 。 此外,集成电路和光集成电路可以在插入器的同一侧上。 通过将光集成电路和集成电路集成在一起,与具有电互连的芯片封装相比,芯片封装可以有助于提高性能。
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公开(公告)号:US20150318254A1
公开(公告)日:2015-11-05
申请号:US14109744
申请日:2013-12-17
IPC分类号: H01L23/00 , H01L25/065
CPC分类号: H01L24/81 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/94 , H01L25/0657 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/03614 , H01L2224/03912 , H01L2224/0401 , H01L2224/0501 , H01L2224/05073 , H01L2224/05082 , H01L2224/05144 , H01L2224/05155 , H01L2224/05644 , H01L2224/11462 , H01L2224/1147 , H01L2224/116 , H01L2224/11849 , H01L2224/1308 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16148 , H01L2224/16227 , H01L2224/16503 , H01L2224/81191 , H01L2224/81193 , H01L2224/8181 , H01L2224/81815 , H01L2224/81825 , H01L2224/94 , H01L2225/06513 , H01L2924/0105 , H01L2924/01322 , H01L2924/2064 , H01L2924/20641 , H01L2924/00014 , H01L2224/03 , H01L2224/11
摘要: This chip package includes a substrate having a gold (or tin) layer disposed on a surface of the substrate. The gold (or tin) layer may couple to a tin (or gold) layer disposed on a surface of a second substrate. When melted, the gold layer and the tin layer result in an interconnect with a chemical composition having a subsequent melting temperature to reflow the bump that is higher than the initial melting temperature. For example, the chemical composition may correspond to a non-equilibrium gold-tin alloy.
摘要翻译: 该芯片封装包括具有设置在基板的表面上的金(或锡)层的基板。 金(或锡)层可以耦合到设置在第二基板的表面上的锡(或金)层。 当熔融时,金层和锡层导致具有随后的熔融温度的化学组成的互连,以使凸起回流高于初始熔融温度。 例如,化学组成可以对应于非平衡金 - 锡合金。
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公开(公告)号:US10591689B2
公开(公告)日:2020-03-17
申请号:US15425887
申请日:2017-02-06
摘要: The disclosed embodiments provide an apparatus for connecting one or more optical fibers to an optoelectronic system. This apparatus includes a packaged optoelectronic module (POeM) comprising an optical connector, a silicon photonic (SiP) chip, an integrated circuit (IC) chip, at least one laser chip and a package substrate. The apparatus also includes an assembly adapter enclosing the POeM, wherein the assembly adapter includes a mechanical transfer (MT) ferrule cavity, which includes one or more coarse-alignment structures to guide an MT ferrule enclosing at least one optical fiber during assembly of the apparatus. The assembly adapter is comprised of a solder-reflow-compatible material to facilitate bonding the assembly adapter to a circuit board.
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