公开(公告)号：US07683434B2

公开(公告)日：2010-03-23

申请号：US12190777

申请日：2008-08-13

申请人： Paul D. Agnello ,  Rajeev Malik ,  K. Paul Muller

发明人： Paul D. Agnello ,  Rajeev Malik ,  K. Paul Muller

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475

摘要： Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.

摘要翻译： 公开了用于防止在半导体器件中的高纵横比介电区域中的空化的方法以及如此形成的器件。 本发明包括在一对结构之间的高纵横比电介质区域中沉积第一电介质，然后移除第一电介质以形成邻近每个结构的支承表面。 轴承表面防止随后填充高纵横比区域的层间电介质的空化。

公开(公告)号：US20080303070A1

公开(公告)日：2008-12-11

申请号：US12190777

申请日：2008-08-13

申请人： Paul D. Agnello ,  Rajeev Malik ,  K. Paul Muller

发明人： Paul D. Agnello ,  Rajeev Malik ,  K. Paul Muller

IPC分类号： H01L29/00

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475

摘要： Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.

摘要翻译： 公开了用于防止在半导体器件中的高纵横比介电区域中的空化的方法以及如此形成的器件。 本发明包括在一对结构之间的高纵横比电介质区域中沉积第一电介质，然后移除第一电介质以形成邻近每个结构的支承表面。 轴承表面防止随后填充高纵横比区域的层间电介质的空化。

公开(公告)号：US07459384B2

公开(公告)日：2008-12-02

申请号：US10710227

申请日：2004-06-28

申请人： Paul D. Agnello ,  Rajeev Malik ,  K. Paul Muller

发明人： Paul D. Agnello ,  Rajeev Malik ,  K. Paul Muller

IPC分类号： H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475

摘要： Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.

摘要翻译： 公开了用于防止在半导体器件中的高纵横比介电区域中的空化的方法以及如此形成的器件。 本发明包括在一对结构之间的高纵横比电介质区域中沉积第一电介质，然后移除第一电介质以形成邻近每个结构的支承表面。 轴承表面防止随后填充高纵横比区域的层间电介质的空化。

公开(公告)号：US07358166B2

公开(公告)日：2008-04-15

申请号：US11208359

申请日：2005-08-19

申请人： Paul D. Agnello ,  Stephen W. Bedell ,  Robert H. Dennard ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Paul D. Agnello ,  Stephen W. Bedell ,  Robert H. Dennard ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L21/205 ,  H01L21/477

CPC分类号： H01L21/324 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66893 ,  H01L29/78603

摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

摘要翻译： 提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。 所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。 将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。 在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

公开(公告)号：US06891228B2

公开(公告)日：2005-05-10

申请号：US10952286

申请日：2004-09-28

申请人： Heemyong Park ,  Byoung H. Lee ,  Paul D. Agnello ,  Dominic J. Schepis ,  Ghavam G. Shahidi

发明人： Heemyong Park ,  Byoung H. Lee ,  Paul D. Agnello ,  Dominic J. Schepis ,  Ghavam G. Shahidi

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/74 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/78612 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/66772

摘要： A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

摘要翻译： CMOS器件的方法和结构包括在掩埋氧化物（BOX）衬底上沉积硅绝缘体（SOI）晶片，其中SOI晶片具有预定厚度; 在所述SOI晶片上形成栅极电介质，在所述BOX衬底上形成浅沟槽隔离（STI）区域，其中所述STI区域被配置为具有大致圆角; 在所述栅极电介质上形成栅极结构; 在SOI晶片上沉积注入层; 在SOI晶片和植入层中执行N型和P型掺杂剂注入之一; 并且从所述注入层和所述SOI晶片听到所述器件以形成源极和漏极区域，其中所述源极和漏极区域具有大于所述SOI晶片的预定厚度的厚度，其中所述栅极电介质位于比所述STI区域低的位置。

公开(公告)号：US06472258B1

公开(公告)日：2002-10-29

申请号：US09711725

申请日：2000-11-13

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

IPC分类号： H01L2130

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66818

摘要： A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

摘要翻译： 场效应晶体管由亚光刻导电沟道和双栅极形成，该双栅极通过简单的工艺由绝缘体上硅晶片开始形成，允许大多数蚀刻工艺使用掩埋氧化物作为蚀刻停止。 通过硅化物侧壁或衬垫实现栅极，源极和漏极的低电阻率，而通过从源极和漏极区域边缘凹陷硅化物和多晶硅双栅极结构来实现低栅极至结电容。

公开(公告)号：US5635242A

公开(公告)日：1997-06-03

申请号：US459261

申请日：1995-06-02

申请人： Paul D. Agnello ,  Thomas O. Sedgwick

发明人： Paul D. Agnello ,  Thomas O. Sedgwick

IPC分类号： C23C16/44 ,  C23C16/455 ,  C23C16/00

CPC分类号： C23C16/45561 ,  C23C16/4401 ,  C23C16/455

摘要： A method of maintaining an optimum pressure and purity level in a vessel having an inlet gas flow and an outlet gas flow during shutdown of the vessel that prevents imploding of the vessel when the inlet and outlet gas flows are discontinued. Gas from the vessel is directed to a containment portion in communication with the vessel. The pressure of the gas in the containment portion is monitored; the containment portion is backfilled with a purified inert gas when the monitored pressure drops to a predetermined lower level; and the containment portion is vented when the monitored pressure rises to a predetermined higher level. Apparatus for maintaining an optimum pressure and purity level in a vessel having an inlet gas flow and an outlet gas flow during shutdown of the vessel that prevents imploding of the vessel when the inlet and outlet gas flows are discontinued is also provided. The apparatus includes a containment portion adjacent to the vessel and in communication with the vessel for containing gas from the vessel, a back-pressure regulator and a conventional regulator for monitoring the pressure of the containment portion, a high-purity inert purge gas source in communication with the conventional regulator, adapted to backfill the containment portion with purified inert gas when the monitored pressure drops to a predetermined lower level, the back-pressure regulator adapted to vent the containment portion when the monitored pressure rises to a predetermined higher level.

摘要翻译： 在停机时，在容器关闭期间保持具有入口气流和出口气流的容器中的最佳压力和纯度水平的方法，其防止当入口气体和出口气体流过时容器内爆。 来自容器的气体被引导到与容器连通的容纳部分。 监测容纳部分中气体的压力; 当监测压力下降到预定的较低水平时，容纳部分用纯化的惰性气体回填; 并且当所监视的压力上升到预定的较高水平时，所述容纳部分被排出。 还提供了用于在容器停止期间具有入口气体流和出口气体流的容器中保持最佳压力和纯度水平的装置，其防止当入口和出口气体流动时中断容器的内泄。 该装置包括与容器相邻并与容器连通的容纳部分，用于容纳来自容器的气体，背压调节器和用于监测容纳部分的压力的常规调节器，高纯度惰性吹扫气体源 与常规调节器通信，适于当监测压力下降到预定的较低水平时用纯化的惰性气体回填容纳部分，背压调节器适于在监测的压力升高到预定的较高水平时排出容纳部分。

公开(公告)号：US07163864B1

公开(公告)日：2007-01-16

申请号：US09691353

申请日：2000-10-18

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

摘要翻译： 通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。 双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

公开(公告)号：US06828630B2

公开(公告)日：2004-12-07

申请号：US10338103

申请日：2003-01-07

申请人： Heemyong Park ,  Byoung H. Lee ,  Paul D. Agnello ,  Dominic J. Schepis ,  Ghavam G. Shahidi

发明人： Heemyong Park ,  Byoung H. Lee ,  Paul D. Agnello ,  Dominic J. Schepis ,  Ghavam G. Shahidi

IPC分类号： H01L2976

CPC分类号： H01L29/78612 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/66772

摘要： A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

摘要翻译： CMOS器件的方法和结构包括在掩埋氧化物（BOX）衬底上沉积硅绝缘体（SOI）晶片，其中SOI晶片具有预定厚度; 在所述SOI晶片上形成栅电介质; 在所述BOX衬底上形成浅沟槽隔离（STI）区域，其中所述STI区域被配置为具有大致圆角; 在所述栅极电介质上形成栅极结构; 在SOI晶片上沉积注入层; 在SOI晶片和植入层中执行N型和P型掺杂剂注入之一; 以及加热所述器件以从所述注入层和所述SOI晶片形成源极和漏极区域，其中所述源极和漏极区域具有大于所述SOI晶片的预定厚度的厚度，其中所述栅极电介质位于所述STI区域之下。

公开(公告)号：US06255217B1

公开(公告)日：2001-07-03

申请号：US09225530

申请日：1999-01-04

申请人： Paul D. Agnello ,  Leena P. Buchwalter ,  John Hummel ,  Barbara Luther ,  Anthony K. Stamper

发明人： Paul D. Agnello ,  Leena P. Buchwalter ,  John Hummel ,  Barbara Luther ,  Anthony K. Stamper

IPC分类号： H01L2144

CPC分类号： H01L21/3185 ,  H01L21/0445 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834

摘要： The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure.

摘要翻译： 本发明利用还原等离子体处理步骤来增强后续沉积的无机阻挡膜对铜线的粘附，或通过存在于诸如双镶嵌结构的半导体互连结构中。