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    APPARATUS AND METHOD OF FORMING METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH ATOMIC LAYER DEPOSITED GATE DIELECTRIC
    1.
    发明申请
    APPARATUS AND METHOD OF FORMING METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH ATOMIC LAYER DEPOSITED GATE DIELECTRIC 审中-公开
    用原子层沉积栅介质形成金属氧化物半导体场效应晶体管的装置和方法

    公开(公告)号：US20080048216A1

    公开(公告)日：2008-02-28

    申请号：US11753993

    申请日：2007-05-25

    申请人： Peide Ye ,  Yi Xuan ,  Han Lin

    发明人： Peide Ye ,  Yi Xuan ,  Han Lin

    IPC分类号： H01L21/335 ,  H01L29/78

    CPC分类号： H01L29/517 ,  H01L21/28264

    摘要： A method for forming a metal oxide semiconductor field-effect transistor (MOSFET) includes forming a III-V compound semiconductor on a substrate with the III-V compound semiconductor being doped with a first dopant type. The method further includes doping a first and second region of the III-V compound semiconductor with a second dopant type to form a drain and a source of the MOSFET. The method further includes forming a gate dielectric on the III-V compound semiconductor through atomic layer deposition. The method further includes applying a metal onto the dielectric to form a gate of the MOSFET. A MOSFET is also disclosed herein.

    摘要翻译： 一种用于形成金属氧化物半导体场效应晶体管（MOSFET）的方法包括在III-V族化合物半导体掺杂有第一掺杂剂型的基板上形成III-V族化合物半导体。 该方法还包括用第二掺杂剂掺杂III-V族化合物半导体的第一和第二区域以形成MOSFET的漏极和源极。 该方法还包括通过原子层沉积在III-V族化合物半导体上形成栅极电介质。 该方法还包括将金属施加到电介质上以形成MOSFET的栅极。 这里也公开了一种MOSFET。

    III-V power field effect transistors
    6.
    发明授权
    III-V power field effect transistors 有权
    III-V功率场效应晶体管

    公开(公告)号：US07180103B2

    公开(公告)日：2007-02-20

    申请号：US10948897

    申请日：2004-09-24

    申请人： Jeff D. Bude ,  Peide Ye ,  Kwok K. Ng ,  Bin Yang

    发明人： Jeff D. Bude ,  Peide Ye ,  Kwok K. Ng ,  Bin Yang

    IPC分类号： H01L29/739 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

    CPC分类号： H01L29/4983 ,  H01L29/812

    摘要： A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.

    摘要翻译： 公开了一种配置用于大功率应用的场效应晶体管及其制造方法。 场效应晶体管由III-V材料形成，并且被配置为具有对大功率应用有利的击穿电压。 通过确定该工作电压的工作电压和期望的击穿电压来配置场效应晶体管。 然后识别与工作电压和期望的击穿电压相关联的峰值电场。 然后将该器件配置为在该工作电压下呈现鉴定的峰值电场。 通过选择控制器件漂移区域中的电位的器件特征来实现该器件的配置。 这些特征包括使用重叠的栅极或场板结合覆盖器件沟道的势垒层，或形成在器件沟道下形成的单晶III-V材料区域中的p型阱。 重叠的栅极/场板或p型阱延伸到器件的漂移区域中，以提供对漂移区域中的电势的期望控制的方式控制器件的电位。

    III-V power field effect transistors
    10.
    发明授权
    III-V power field effect transistors 失效
    III-V功率场效应晶体管

    公开(公告)号：US07537984B2

    公开(公告)日：2009-05-26

    申请号：US11641507

    申请日：2006-12-19

    申请人： Jeff D. Bude ,  Peide Ye ,  Kwok K. Ng ,  Bin Yang

    发明人： Jeff D. Bude ,  Peide Ye ,  Kwok K. Ng ,  Bin Yang

    IPC分类号： H01L21/338

    CPC分类号： H01L29/4983 ,  H01L29/812

    摘要： A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.

    摘要翻译： 公开了一种配置用于大功率应用的场效应晶体管及其制造方法。 场效应晶体管由III-V材料形成，并且被配置为具有对大功率应用有利的击穿电压。 通过确定该工作电压的工作电压和期望的击穿电压来配置场效应晶体管。 然后识别与工作电压和期望的击穿电压相关联的峰值电场。 然后将该器件配置为在该工作电压下呈现鉴定的峰值电场。 通过选择控制器件漂移区域中的电位的器件特征来实现该器件的配置。 这些特征包括使用重叠的栅极或场板结合覆盖器件沟道的势垒层，或形成在器件沟道下形成的单晶III-V材料区域中的p型阱。 重叠的栅极/场板或p型阱延伸到器件的漂移区域中，以提供对漂移区域中的电势的期望控制的方式控制器件的电位。