摘要:
An integrated circuit having an array of memory cells is disclosed. One embodiment provides selection transistors for selecting one of a plurality of memory cells. The selection transistor is a tunnel field effect transistor in order to reduce a leakage current when the transistor is in its non-conducting state. Furthermore an operation method and a method for production are described.
摘要:
A transistor which can in particular be used in memory cells of a Dynamic Random Access Memory a memory cell and a method of manufacturing a transistor is disclosed. In one embodiment the transistor is a dual-fin field effect transistor. The transistor includes a first and a second source/drain regions, a channel connecting the first and second source/drain regions, a gate electrode for controlling an electrical current flowing between the first and second source/drain regions. The gate electrode is insulated from the channel by a gate dielectric, wherein the gate electrode is disposed in a gate groove extending in the substrate surface so that the channel comprises two fin-like channel portions extending between the first and second source/drain regions in a cross-sectional view taken perpendicularly to a line connecting the first and the second source/drain regions, the gate electrode delimiting each of the fin-like channel portions at one side thereof.
摘要:
An integrated circuit includes a transistor of a first type with a first gate electrode and a transistor of a second type with a second gate electrode. The first gate electrode is formed in a first gate groove that is defined in a semiconductor substrate, and the second gate electrode is formed in a second gate groove defined in the semiconductor substrate. The first gate electrode completely fills a space between two adjacent first isolation trenches, and the second gate electrode partially fills a space between two adjacent second isolation trenches, with substrate portions being arranged between the second gate electrode and the adjacent second isolation trenches, respectively.
摘要:
An integrated circuit includes a plurality of memory cells, each memory cell including a memory element and a select device; and a plurality of word lines and bit lines connected to the memory cells. The bit lines, word lines, and the memory elements are arranged above the select devices.
摘要:
The present invention provides an integrated circuit with a floating body transistor comprising two source/drain regions and a floating body region arranged between the two source/drain regions comprising: a back gate electrode separated from the floating body by a first dielectric layer; a control gate electrode, separated from the floating body by a second dielectric layer and overlying the back gate electrode; and a third dielectric layer arranged between the back gate electrode and the control gate electrode. The present invention provides also a method of manufacturing an integrated circuit and a method of operating an integrated circuit.
摘要:
A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and the interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.
摘要:
This invention relates to an organic electroluminescence (EL) device and to the use of a tris-cyclometalated iridium complex with a 3-Phenyl-azine ligand for thin-film type organic electroluminescence devices.The iridium complexes used have the following formulae:
摘要:
An integrated circuit includes a transistor of a first type with a first gate electrode and a transistor of a second type with a second gate electrode. The first gate electrode is formed in a first gate groove that is defined in a semiconductor substrate, and the second gate electrode is formed in a second gate groove defined in the semiconductor substrate. The first gate electrode completely fills a space between two adjacent first isolation trenches, and the second gate electrode partially fills a space between two adjacent second isolation trenches, with substrate portions being arranged between the second gate electrode and the adjacent second isolation trenches, respectively.
摘要:
The present invention is related to microelectronic technologies, and discloses specifically a dynamic random access memory (DRAM) array and methods of making the same. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices. The present invention also provides a method of making a DRAM array.
摘要:
A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.