摘要:
Semiconductor devices and conductive structures can be formed having a metallic layer. In one embodiment, a semiconductor device includes an amorphous metallic layer (22) and a crystalline metallic layer (42). The amorphous metallic layer (22) helps to reduce the likelihood of penetration of contaminants through the amorphous metallic layer (22). A more conductive crystalline metallic layer (42) can be formed on the amorphous metallic layer (22) to help keep resistivity relatively low. When forming a conductive structure, a metal-containing gas and a scavenger gas flow simultaneously during at least one point in time. The conductive structure may be part of a gate electrode.
摘要:
Metal semiconductor nitride gate electrodes (40, 70) are formed for use in a semiconductor device (60). The gate electrodes (40, 70) may be formed by sputter deposition, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The materials are expected to etch similar to silicon-containing compounds and may be etched in traditional halide-based etching chemistries. The metal semiconductor nitride gate electrodes (40, 70) are relatively stable, can be formed relatively thinner than traditional gate electrodes (40, 70) and work functions near the middle of the band gap for the material of the substrate (12).
摘要:
In one embodiment a non-volatile memory device having improved reliability is formed by oxidizing a first portion of a semiconductor substrate (12) to form a first silicon dioxide layer (14). The first silicon dioxide layer (14) is then annealed and second portion of the silicon substrate, underlying the annealed silicon dioxide layer (16), is then oxidized to form a second silicon dioxide layer (18). The annealed silicon dioxide layer (16) and the second silicon dioxide layer (18) form a pre-oxide layer (20). The pre-oxide layer (20) is then nitrided to form a nitrided oxide dielectric layer (22). A floating gate is then formed overlying the nitrided oxide dielectric layer (22), which serves as the tunnel oxide for the device. Tunnel oxides formed with the inventive process are less susceptible to stress-induced leakage, and therefore, devices with improved data retention and endurance may be fabricated.
摘要:
A process for reducing halogen concentration in a material layer (56) includes the deposition of a dielectric layer (58) overlying the material layer (56). An annealing process is carried out to diffuse halogen atoms from the material layer (56) into the overlying dielectric layer (58). Once the diffusion process is complete, the dielectric layer (58) is removed.
摘要:
A first metal-containing material (22) is formed over a semiconductor device substrate (10). A second metal-containing material (32) is formed over the first metal containing material (22). The combination of the second metal-containing material (32) formed over the first metal-containing material (22) forms a metal stack (34). The metal stack (34) is annealed and a post-anneal stress of the metal stack (34) is less than an individual post-anneal stress of either one of the first conductive film (22) or the second conductive film (32).
摘要:
A method for forming a metal gate (20) structure begins by providing a semiconductor substrate (12). The semiconductor substrate (12) is cleaned to reduce trap sites. A nitrided layer (14) having a thickness of less than approximately 20 Angstroms is formed over the substrate (12). This nitrided layer prevents the formation of an oxide at the substrate interface and has a dielectric constant greater than 3.9. After the formation of the nitrided layer(14), a metal oxide layer (16) having a permittivity value of greater than roughly 8.0 is formed over the nitrided layer (14). A metal gate (20) is formed over the nitrided layer whereby the remaining composite gate dielectric (14 and 16) has a larger physical thickness but a high-performance equivalent oxide thickness (EOT).
摘要:
In one embodiment, a metal layer (18) is formed over a gate dielectric layer (14, 16) on a semiconductor substrate. A masking layer (20) is patterned to mask a portion of the metal layer (18). An exposed portion of the metal layer (18) is nitrided to form a conductive nitride layer (24). The masking layer (20) is removed and the conductive nitride layer (24) is patterned to form a first gate electrode (23) having a first work function value, and the conductive layer (18) is patterned to form a second gate electrode (25) having a second work function value which is different from that of the first work function value.
摘要:
A read-only memory for storing two data values using a single transistor includes a word line, a pair of bit lines, a select line, and a transistor to store data corresponding to each bit lines in the pair of bit lines. The gate terminal of the transistor is connected to the word line, a first diffusion terminal of the transistor is connected to one of the first bit line and the select line based on the first data value and a second diffusion terminal of the transistor is connected to one of the second bit line and the select line based on the second data value.
摘要:
First and second dummy structures (201 and 202) are formed over a semiconductor device substrate (10). In one embodiment, portions of the first dummy structure (201) are removed and replaced with a first conductive material (64) to form a first gate electrode (71) and portions of second dummy structure (202) are removed and replaced with a second conductive material (84) to form a second gate electrode (91). In an alternate embodiment, the dummy structures (201 and 202) are formed using a first conductive material (164) that is used to form the first electrode (71). The second electrode is then formed by removing the first conductive material (164) from dummy structures (202) and replacing it with a second conductive material (84). In accordance with embodiments of the present invention, the first conductive material and the second conductive material are different conductive materials.
摘要:
A memory device includes a memory array, sense circuitry coupled to the memory array, and timing circuitry coupled to the sense circuitry. The timing circuitry generates a sense trigger signal to enable the sense circuitry. A strap region is formed adjacent the memory array. A reference word line is coupled to the timing circuitry. The reference word line formed in the strap region.