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公开(公告)号：US08788737B2
公开(公告)日：2014-07-22
申请号：US13337280
申请日：2011-12-26
IPC分类号： G06F13/36
CPC分类号： G06F13/4022 , G06F13/405
摘要： A system and method are disclosed for connecting PCI-ordered agents based on fully independent networks. The system and method are free of PCI topology constraints, so that the system and method can be implemented in an inexpensive and scalable way. The method disclosed is used to handle and transport PCI-ordered traffic on a fabric. Based on the actual ordering requirement of the set of PCI agents, the fabric includes two, three, or four independent networks.
摘要翻译： 公开了一种用于连接基于完全独立网络的PCI有序代理的系统和方法。 该系统和方法没有PCI拓扑约束，从而可以以便宜且可扩展的方式实现系统和方法。 所公开的方法用于在结构上处理和传输PCI-有序流量。 基于一组PCI代理的实际排序要求，该架构包括两个，三个或四个独立网络。
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公开(公告)号：US20110302345A1
公开(公告)日：2011-12-08
申请号：US12835623
申请日：2010-07-13
IPC分类号： G06F13/368
CPC分类号： G06F13/362 , H04L45/302 , H04L47/10 , H04L47/2441 , H04L47/2458 , H04L49/10 , H04L49/109 , H04L49/205
摘要： Quality-of-Service (QoS) is an important system-level requirement in the design and implementation of on-chip networks. QoS requirements can be implemented in an on-chip-interconnect by providing for at least two signals indicating priority at a transaction-level interface where one signal transfers information in-band with the transaction and the other signal transfers information out-of-band with the transaction. The signals can be processed by the on-chip-interconnect to deliver the required QoS. In addition, the disclosed embodiments can be extended to a Network-on-Chip (NoC).
摘要翻译： 服务质量（QoS）是片上网络设计和实现中的重要系统级要求。 QoS要求可以通过提供至少两个表示交易级别接口处的优先级的信号来实现，其中一个信号在事务处理带内传输信息，另一个信号在带外传输信息， 交易。 这些信号可以通过片上互连来处理以提供所需的QoS。 另外，所公开的实施例可以扩展到片上网络（NoC）。
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公开(公告)号：US08316171B2
公开(公告)日：2012-11-20
申请号：US12835623
申请日：2010-07-13
IPC分类号： G06F13/14
CPC分类号： G06F13/362 , H04L45/302 , H04L47/10 , H04L47/2441 , H04L47/2458 , H04L49/10 , H04L49/109 , H04L49/205
摘要： Quality-of-Servitrce (QoS) is an important system-level requirement in the design and implementation of on-chip networks. QoS requirements can be implemented in an on-chip-interconnect by providing for at least two signals indicating priority at a transaction-level interface where one signal transfers information in-band with the transaction and the other signal transfers information out-of-band with the transaction. The signals can be processed by the on-chip-interconnect to deliver the required QoS. In addition, the disclosed embodiments can be extended to a Network-on-Chip (NoC).
摘要翻译： 服务质量（QoS）是片上网络设计和实现中的重要系统级要求。 QoS要求可以通过提供至少两个表示交易级别接口处的优先级的信号来实现，其中一个信号在事务处理带内传输信息，另一个信号在带外传输信息， 交易。 这些信号可以通过片上互连来处理以提供所需的QoS。 另外，所公开的实施例可以扩展到片上网络（NoC）。
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公开(公告)号：US20110085550A1
公开(公告)日：2011-04-14
申请号：US12579346
申请日：2009-10-14
IPC分类号： H04L12/28
CPC分类号： H04L49/3072 , G06F13/4009 , G06F2213/0038 , H04L45/245 , H04L47/10 , H04L49/109 , H04L69/22 , Y02B70/30 , Y02D50/30
摘要： Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.
摘要翻译： 通过使用至少两个独立参数：一个控制数据宽度的参数和一个控制延迟处罚的参数的参数，扩展了对于在知识产权（IP）核心互连的物理链路上传输的数据包的数据包格式可配置性。 至少两个独立参数允许创建传输协议分组，而不需要额外的延迟插入，这对于低延迟应用是有用的。 至少两个独立参数还允许创建具有多周期附加延迟的窄分组，这对延迟容忍的区域敏感应用是有用的。
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5.发明授权公开(公告)号：US09069912B2
公开(公告)日：2015-06-30
申请号：US13436944
申请日：2012-03-31
CPC分类号： G06F13/4059 , G06F13/22 , G06F13/4031
摘要： A Network-on-Chip (NoC) is provided that performs reordering of transaction responses such as those with requests that cross address mapping boundaries. Ordering is ensured by filtering logic in reorder buffers, some of which include storage to allow multiple simultaneously pending transactions. Transactions are transported by a packet-based transport protocol. The reorder buffering is done at packet level, within the transport topology. Reorder buffers are distributed physically throughout the floorplan of the chip, they have localized connectivity to initiators, and they operate in separate power and clock domains.
摘要翻译： 提供了片上网络（NoC），其执行诸如具有跨地址映射边界的请求的事务响应的重新排序。 通过在重排序缓冲区中过滤逻辑来确保排序，其中一些包括存储以允许多个同时挂起的事务。 事务通过基于分组的传输协议传送。 重新排序缓冲在传输拓扑中的分组级完成。 重新排序缓冲区物理地分布在芯片的整个平面图中，它们具有到启动器的本地化连接，并且它们在单独的电源和时钟域中操作。
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公开(公告)号：US20120290810A1
公开(公告)日：2012-11-15
申请号：US13450342
申请日：2012-04-18
IPC分类号： G06F12/02
CPC分类号： G06F13/1689
摘要： Memory transactions that are issued just in time have deterministic response delay. By measuring an actual delay and comparing it to an expected delay a memory scheduler can determine whether it is issuing transaction requests too early and can thereby automatically adapt the issue of transaction requests by delaying future transaction requests to be just in time.
摘要翻译： 刚刚发布的内存事务具有确定性的响应延迟。 通过测量实际延迟并将其与期望的延迟进行比较，存储器调度器可以确定它是否过早地发出事务请求，并且因此可以通过将未来的事务请求延迟到及时来自动地调整事务请求的问题。
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7.发明授权Digital delay device, digital oscillator clock signal generator and memory interface 失效数字延时器，数字振荡器时钟信号发生器和存储器接口公开(公告)号：US07148728B2
公开(公告)日：2006-12-12
申请号：US10957211
申请日：2004-10-01
IPC分类号： H03L7/06
CPC分类号： H03K5/131 , H03K3/0315 , H03K5/133 , H03L7/0814 , H03L7/0818 , H03L7/0995
摘要： Digitally controlled delay device, including a plurality of fine delay elements and a plurality of coarse delay elements, capable of delaying a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays and the sum of the fine delay times being greater than or equal to at least one coarse delay.
摘要翻译： 数字控制的延迟装置包括多个精细延迟元件和多个粗略的延迟元件，它们能够分别延迟由器件产生的信号，细微或延迟延迟，具有60到170之间的延迟时间的精细延迟元件 精细延迟的平均值的百分比和精细延迟时间的总和大于或等于至少一个粗略的延迟。
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公开(公告)号：US09049124B2
公开(公告)日：2015-06-02
申请号：US12579346
申请日：2009-10-14
IPC分类号： G06F3/00 , H04L12/28 , H04L12/801 , H04L12/709 , H04L12/933 , G06F13/40
CPC分类号： H04L49/3072 , G06F13/4009 , G06F2213/0038 , H04L45/245 , H04L47/10 , H04L49/109 , H04L69/22 , Y02B70/30 , Y02D50/30
摘要： Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.
摘要翻译： 通过使用至少两个独立参数：一个控制数据宽度的参数和一个控制延迟处罚的参数的参数，扩展了对于在知识产权（IP）核心互连的物理链路上传输的数据包的数据包格式可配置性。 至少两个独立参数允许创建传输协议分组，而不需要额外的延迟插入，这对于低延迟应用是有用的。 至少两个独立参数还允许创建具有多周期附加延迟的窄分组，这对延迟容忍的区域敏感应用是有用的。
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9.发明申请Digital delay device, digital oscillator clock signal generator and memory interface 失效数字延时器，数字振荡器时钟信号发生器和存储器接口公开(公告)号：US20050104644A1
公开(公告)日：2005-05-19
申请号：US10957211
申请日：2004-10-01
CPC分类号： H03K5/131 , H03K3/0315 , H03K5/133 , H03L7/0814 , H03L7/0818 , H03L7/0995
摘要： Digitally controlled delay device, including a plurality of fine delay elements and a plurality of coarse delay elements, capable of delaying a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays and the sum of the fine delay times being greater than or equal to at least one coarse delay.
摘要翻译： 数字控制的延迟装置包括多个精细延迟元件和多个粗略的延迟元件，它们能够分别延迟由器件产生的信号，细微或延迟延迟，具有60到170之间的延迟时间的精细延迟元件 精细延迟的平均值的百分比和精细延迟时间的总和大于或等于至少一个粗略的延迟。
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公开(公告)号：US20120331034A1
公开(公告)日：2012-12-27
申请号：US13528780
申请日：2012-06-20
申请人： Alain Fawaz , Philippe Boucard , Philippe Martin
发明人： Alain Fawaz , Philippe Boucard , Philippe Martin
IPC分类号： G06F15/16
CPC分类号： G06F11/3419 , G06F11/34 , G06F11/349 , G06F13/385 , G06F2201/81 , G06F2201/87 , G06F2201/88
摘要： A probe within a Network-on-Chip (NoC) that can calculate a histogram of transaction data is disclosed. Some such histograms are cycles per number of pending transactions, transactions per latency, and transactions per request delay. The number of pending transactions can be measured by a register that is incremented at the start and decremented at the end of each transaction. Latencies can be measured by timers that are allocated and initialized at the start and read at the end of each transaction. Multiple counters can be used for multiple pending transactions. Multiple banks of counters can be used so that multiple transaction interfaces can complete transactions and perform histogram bin threshold comparisons simultaneously. The thresholds separating histogram bins can be programmable.
摘要翻译： 披露了可以计算事务数据直方图的片上网络（NoC）中的探测器。 一些这样的直方图是每个待处理事务的数量，每个延迟的事务和每个请求延迟的事务的周期。 待处理交易的数量可以通过在开始时递增并在每个交易结束时递减的寄存器来衡量。 延迟可以通过在开始时分配和初始化并在每个事务结束时读取的定时器来测量。 多个计数器可用于多个待处理事务。 可以使用多个计数器组，以便多个事务接口可以完成事务并同时执行直方图bin阈值比较。 分离柱状图仓的阈值可以是可编程的。
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