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公开(公告)号：US06889429B2
公开(公告)日：2005-05-10
申请号：US09817330
申请日：2001-03-26
IPC分类号： H01L23/14 , H01L23/498 , H05K3/24 , H05K3/34
CPC分类号： H05K3/243 , H01L23/145 , H01L23/49811 , H01L23/49827 , H01L24/48 , H01L2224/05554 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/8547 , H01L2924/00014 , H01L2924/01078 , H01L2924/14 , H01L2924/15173 , H01L2924/15183 , H01L2924/15312 , H01L2924/181 , H05K3/3436 , H05K3/3452 , H05K2201/0367 , H05K2203/0574 , Y02P70/613 , Y10T29/4913 , Y10T29/49139 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T29/49169 , Y10T29/49171 , Y10T29/49172 , Y10T29/53204 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.
摘要翻译： 集成电路封装（60）具有基板（12），其具有用于安装半导体管芯（20）的第一表面（51）和限定通孔（70）的第二表面（52）。 通过电镀导电材料从第二表面向外突出而形成引线（26）。 导电材料从引线延伸穿过第一通孔以耦合到半导体管芯。
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公开(公告)号：US07180170B2
公开(公告)日：2007-02-20
申请号：US11040334
申请日：2005-01-24
CPC分类号： H05K3/243 , H01L23/145 , H01L23/49811 , H01L23/49827 , H01L24/48 , H01L2224/05554 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/8547 , H01L2924/00014 , H01L2924/01078 , H01L2924/14 , H01L2924/15173 , H01L2924/15183 , H01L2924/15312 , H01L2924/181 , H05K3/3436 , H05K3/3452 , H05K2201/0367 , H05K2203/0574 , Y02P70/613 , Y10T29/4913 , Y10T29/49139 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T29/49169 , Y10T29/49171 , Y10T29/49172 , Y10T29/53204 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.
摘要翻译： 集成电路封装（60）具有基板（12），其具有用于安装半导体管芯（20）的第一表面（51）和限定通孔（70）的第二表面（52）。 通过电镀导电材料从第二表面向外突出而形成引线（26）。 导电材料从引线延伸穿过第一通孔以耦合到半导体管芯。
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3.发明授权公开(公告)号：US06833290B2
公开(公告)日：2004-12-21
申请号：US10374630
申请日：2003-02-27
IPC分类号： H01L23495
CPC分类号： H01L24/49 , H01L23/3107 , H01L23/3135 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4903 , H01L2224/49051 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01039 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12041 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device (20) has a first leadframe (200) with a first semiconductor die (70) electrically coupled to one of its leads. A second semiconductor die (130) is mounted to a second leadframe (300) that has a first lead (35, 150) electrically coupled to the second semiconductor die and a second lead (30, 35) mounted to the lead of the first leadframe.
摘要翻译： 半导体器件（20）具有第一引线框架（200），其具有与其引线之一电耦合的第一半导体管芯（70）。 第二半导体管芯（130）安装到具有电耦合到第二半导体管芯的第一引线（35,150）和安装到第一引线框架的引线上的第二引线（30,35）的第二引线框架（300） 。
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公开(公告)号：US06677672B2
公开(公告)日：2004-01-13
申请号：US10133527
申请日：2002-04-26
IPC分类号： H01L2322
CPC分类号： H01L24/49 , H01L23/3107 , H01L23/3135 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4903 , H01L2224/49051 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01039 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12041 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device (20) has a first leadframe (200) with a first semiconductor die (70) electrically coupled to one of its leads. A second semiconductor die (130) is mounted to a second leadframe (300) that has a first lead (35, 150) electrically coupled to the second semiconductor die and a second lead (30, 35) mounted to the lead of the first leadframe.
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公开(公告)号：US6103548A
公开(公告)日：2000-08-15
申请号：US931982
申请日：1997-09-17
IPC分类号： H01L23/498 , H01L21/20
CPC分类号： H01L23/49838 , H01L24/49 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/4847 , H01L2224/49 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107
摘要： A semiconductor device includes a substrate (10) that can be cut into different sizes. A plurality of wirebond fingers (12) are formed on a top surface (13) of the substrate (10). The plurality of wirebond fingers (12) are located within concentric interconnect regions (23, 25, 27, 29, 31, 33, 35) and electrically connected to a via (14) by a signal interconnect line (11). The size of substrate (10) can be altered by cutting the substrate (10) to remove any of the interconnect regions (23, 25, 27, 29, 31, 33, 35). A semiconductor component (44) attached to the top side (13) of the substrate (10) can have a die pad (48) wirebonded to any of the plurality of wirebond fingers (12) located along the signal interconnect line (11) for connection to the via (14).
摘要翻译： 半导体器件包括可被切割成不同尺寸的衬底（10）。 多个引线键（12）形成在基板（10）的顶表面（13）上。 多个引线键指（12）位于同心互连区（23,25,27,29,31,33,35）内，并通过信号互连线（11）与通孔（14）电连接。 可以通过切割衬底（10）以去除任何互连区域（23,25,27,29,31,33,35）来改变衬底（10）的尺寸。 附接到基板（10）的顶侧（13）的半导体部件（44）可以具有引线接合到沿着信号互连线（11）定位的多个引线键指（12）中的任何一个的芯片焊盘（48），用于 与通孔（14）的连接。
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