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    EXTENDING DRIVE CAPABILITY IN INTEGRATED CIRCUITS UTILIZING PROGRAMMABLE-VOLTAGE OUTPUT CIRCUITS
    1.
    发明申请
    EXTENDING DRIVE CAPABILITY IN INTEGRATED CIRCUITS UTILIZING PROGRAMMABLE-VOLTAGE OUTPUT CIRCUITS 有权
    使用可编程电压输出电路的集成电路中扩展驱动能力

    公开(公告)号：US20090167357A1

    公开(公告)日：2009-07-02

    申请号：US11967885

    申请日：2007-12-31

    申请人： Po-Shen Lai ,  Vaibhavi Sabharanjak ,  Ralph Heron ,  Lakhdar Iguelmamene

    发明人： Po-Shen Lai ,  Vaibhavi Sabharanjak ,  Ralph Heron ,  Lakhdar Iguelmamene

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018585 ,  H03K19/017581

    摘要： An integrated circuit (IC) includes an output driver circuit portion that is electrically configurable, via a configuration input, to operate in either a first mode or a second mode corresponding to an indication of a condition of the IC, such as a supply voltage indication, the first mode and the second mode having different drive characteristics. A configuration interface circuit portion as part of the improved IC is adapted to selectively override the configuration input to configure operation of the output driver circuit portion in either the first mode or the second mode based on a drive strength control input, regardless of the condition of the IC.

    摘要翻译： 集成电路（IC）包括输出驱动器电路部分，其经由配置输入可电气配置，以对应于IC的状态的指示的第一模式或第二模式操作，诸如电源电压指示 第一模式和第二模式具有不同的驱动特性。 作为改进IC的一部分的配置接口电路部分适于选择性地覆盖配置输入以基于驱动强度控制输入来配置在第一模式或第二模式中的输出驱动器电路部分的操作，而不管 IC。

    Extending drive capability in integrated circuits utilizing programmable-voltage output circuits
    2.
    发明授权
    Extending drive capability in integrated circuits utilizing programmable-voltage output circuits 有权
    利用可编程电压输出电路在集成电路中扩展驱动能力

    公开(公告)号：US07812639B2

    公开(公告)日：2010-10-12

    申请号：US11967885

    申请日：2007-12-31

    申请人： Po-Shen Lai ,  Vaibhavi Sabharanjak ,  Ralph Heron ,  Lakhdar Iguelmamene

    发明人： Po-Shen Lai ,  Vaibhavi Sabharanjak ,  Ralph Heron ,  Lakhdar Iguelmamene

    IPC分类号： H03K19/094

    CPC分类号： H03K19/018585 ,  H03K19/017581

    摘要： An integrated circuit (IC) includes an output driver circuit portion that is electrically configurable, via a configuration input, to operate in either a first mode or a second mode corresponding to an indication of a condition of the IC, such as a supply voltage indication, the first mode and the second mode having different drive characteristics. A configuration interface circuit portion as part of the improved IC is adapted to selectively override the configuration input to configure operation of the output driver circuit portion in either the first mode or the second mode based on a drive strength control input, regardless of the condition of the IC.

    摘要翻译： 集成电路（IC）包括输出驱动器电路部分，其经由配置输入可电气配置，以对应于IC的状态的指示的第一模式或第二模式操作，诸如电源电压指示 第一模式和第二模式具有不同的驱动特性。 作为改进IC的一部分的配置接口电路部分适于选择性地覆盖配置输入以基于驱动强度控制输入来配置在第一模式或第二模式中的输出驱动器电路部分的操作，而不管 IC。

    Multi-regulator power delivery system for ASIC cores
    5.
    发明申请
    Multi-regulator power delivery system for ASIC cores 有权
    用于ASIC内核的多调节器供电系统

    公开(公告)号：US20090160421A1

    公开(公告)日：2009-06-25

    申请号：US12005144

    申请日：2007-12-21

    申请人： Daniel P. Nguyen ,  Steve X. Chi ,  Po-Shen Lai

    发明人： Daniel P. Nguyen ,  Steve X. Chi ,  Po-Shen Lai

    IPC分类号： G05B24/02 ,  G05F1/10

    CPC分类号： H02M1/36 ,  G11C16/30 ,  H02M2001/0032 ,  H02M2001/0045 ,  Y02B70/16 ,  Y10T307/696

    摘要： An electronic product includes an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product. Control logic of the ASIC device is responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation.

    摘要翻译： 电子产品包括专用半导体芯片（ASIC）器件，其在其电路中包括被配置为耦合到可选外部电容的线性调节器模块和被配置为耦合到电子产品的内部电容的无电容调节器模块。 ASIC设备的控制逻辑响应于调节器选择信号，用于选择线性调节器模块和无限幅调节器模块之一，以用于为ASIC设备供电。 控制逻辑可以在某些操作时间内选择线性调节器模块，并在其他操作时间内选择无限幅调节器模块。

    Apparatus and method in a network interface device for determining data availability in a random access memory
    6.
    发明授权
    Apparatus and method in a network interface device for determining data availability in a random access memory 有权
    一种用于确定随机存取存储器中的数据可用性的网络接口设备中的装置和方法

    公开(公告)号：US06789144B1

    公开(公告)日：2004-09-07

    申请号：US09320579

    申请日：1999-05-27

    申请人： Po-Shen Lai ,  Autumn J. Niu

    发明人： Po-Shen Lai ,  Autumn J. Niu

    IPC分类号： G06F500

    CPC分类号： G06F5/12 ,  G06F2205/067 ,  G06F2205/108 ,  G06F2205/126

    摘要： A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data between a host computer bus and a packet switched network. The network interface device includes a memory controller that determines whether a complete frame is stored in the random access memory and also determines an amount of data available to be read from the oldest received frame. A host CPU is able to access this information and determine whether to read the data or read the data at a later time.

    摘要翻译： 网络接口设备包括用作发送和接收缓冲器的随机存取存储器，用于在主计算机总线和分组交换网络之间传输和接收数据。 网络接口设备包括一个存储器控制器，该存储器控制器确定一个完整帧是否存储在随机存取存储器中，并且还确定可用于从最早接收帧读取的数据量。 主机CPU能够访问该信息，并确定是否读取数据或稍后读取数据。

    Apparatus and method in a network interface device for storing tracking information indicating stored data status between contending memory controllers
    7.
    发明授权
    Apparatus and method in a network interface device for storing tracking information indicating stored data status between contending memory controllers 失效
    网络接口装置中的设备和方法，用于存储指示存储在竞争存储器控制器之间的数据状态的跟踪信息

    公开(公告)号：US6061768A

    公开(公告)日：2000-05-09

    申请号：US993891

    申请日：1997-12-18

    申请人： Jerry Chun-Jen Kuo ,  Autumn Jane Niu ,  Po-Shen Lai

    发明人： Jerry Chun-Jen Kuo ,  Autumn Jane Niu ,  Po-Shen Lai

    IPC分类号： G06F13/38 ,  G06F13/00

    CPC分类号： G06F13/387

    摘要： A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. The determined presence of one or more stored data frames is used to arbitrate storage of tracking information by either the read controller or the write controller into a holding register used to determine a read status for the random access memory.

    摘要翻译： 网络接口设备包括用作发送和接收缓冲器的随机存取存储器，用于在主计算机总线和分组交换网络之间传输和接收数据帧。 网络接口设备包括用于每个发送和接收缓冲器的读和写控制器，其中每个写控制器在与相应的读控制器分离的时钟域中操作。 存储器管理单元还包括同步电路，其控制仲裁以访问读取和写入控制器之间的随机存取存储器。 同步电路通过异步比较存储在灰度代码计数器中的写入计数器和读取计数器值来确定随机存取存储器中存储的帧的存在，其中每个计数器被配置为响应于增量信号来改变计数器值的单个位 。 所确定的一个或多个存储的数据帧的存在被用于将读取控制器或写入控制器的跟踪信息的存储仲裁为用于确定随机存取存储器的读取状态的保持寄存器。

    Exclusive-option chips and methods with all-options-active test mode
    8.
    发明授权
    Exclusive-option chips and methods with all-options-active test mode 有权
    独家选项芯片和方法，具有全选项活动测试模式

    公开(公告)号：US08558566B2

    公开(公告)日：2013-10-15

    申请号：US13089093

    申请日：2011-04-18

    申请人： Po-Shen Lai ,  Paul A. Lassa ,  Paul C. Paternoster

    发明人： Po-Shen Lai ,  Paul A. Lassa ,  Paul C. Paternoster

    IPC分类号： G01R31/3187 ,  G01R31/02 ,  G01R31/28 ,  G01R31/319 ,  G01R31/3185

    CPC分类号： G01R31/2884 ,  G01R31/318511 ,  G01R31/318558 ,  G01R31/31924

    摘要： A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.

    摘要翻译： 一种多接口集成电路，其中在芯片使用寿命期间，一次只有一个接口处于活动状态。 但是，特殊的测试逻辑可以一次启动所有片上接口模块，从而可以执行完整的测试周期。 所有接口都在一个测试程序中执行。 由于某些接口模式下某些焊盘无效，因此使用掩码位来选择在哪个测试周期内监视哪些焊盘。

    Apparatus and method in a network interface for recovering from complex PCI bus termination conditions
    10.
    发明授权
    Apparatus and method in a network interface for recovering from complex PCI bus termination conditions 有权
    网络接口中的装置和方法，用于从复杂的PCI总线终端状况恢复

    公开(公告)号：US06216193B1

    公开(公告)日：2001-04-10

    申请号：US09146252

    申请日：1998-09-03

    申请人： Po-Shen Lai ,  Autumn Jane Niu ,  Jerry Chun-Jen Kuo ,  John M. Chiang

    发明人： Po-Shen Lai ,  Autumn Jane Niu ,  Jerry Chun-Jen Kuo ,  John M. Chiang

    IPC分类号： G06F1300

    CPC分类号： G06F13/385

    摘要： A network interface includes a multiplexer that selectively supplies either a stored address from an address holding register, or a reload address from a reload address holding register, to a random access buffer memory based on a done delay signal (DMA_DONE_DLY). The done delay signal is generated by an advance signal generator in response to detection of a target initiated termination request on the PCI bus during a DMA data transfer from the random access buffer memory to the target. if the PCI bus transfer is interrupted, the reload address is supplied to the random access buffer memory to enable data output holding registers to be reloaded with the data lost by the target during the interrupted DMA transfer. The array of data output holding registers are capable of recovering from the interrupted PCI bus transfer and output the data set which the target (e.g., the host system memory) expects to receive. The reload address is also supplied to the address register to resume normal addressing by address holding register.

    摘要翻译： 网络接口包括多路复用器，其基于完成的延迟信号（DMA_DONE_DLY），将存储的地址从地址保持寄存器或重载地址从重载地址保持寄存器选择性地提供给随机存取缓冲存储器。 响应于在从随机存取缓冲存储器到目标的DMA数据传输期间在PCI总线上检测到目标发起的终止请求，由提前信号发生器产生完成的延迟信号。 如果PCI总线传输中断，则重新加载地址被提供给随机存取缓冲存储器，以使数据输出保持寄存器在DMA中断期间由目标丢失的数据重新加载。 数据输出保持寄存器阵列能够从中断的PCI总线传送恢复，并输出目标（例如，主机系统存储器）期望接收的数据集。 重载地址也提供给地址寄存器，以通过地址保持寄存器恢复正常寻址。