公开(公告)号：US20250079337A1

公开(公告)日：2025-03-06

申请号：US18460863

申请日：2023-09-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jonghae Kim ,  Bin Yang ,  Giridhar Nallapati

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

Abstract: An integrated circuit (IC) includes a plurality of first metallization layers on a front side of a circuit layer and a plurality of second metallization layers on a back side of the circuit layer. A semiconductor substrate on the back side of the circuit layer of the IC is thinned to improve access to devices from the back side. The plurality of second metallization layers are employed to provide increased interconnection among the devices without increasing area and may provide increased access to external contacts. Thinning the semiconductor substrate reduces structural rigidity needed for processing, so the IC also includes a stiffening layer on one of the plurality of first metallization layers and the plurality of second metallization layers to increase rigidity and first vias extending through the stiffening layer to couple to first contacts.

公开(公告)号：US12206155B2

公开(公告)日：2025-01-21

申请号：US18189684

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Kai Liu ,  Jonghae Kim ,  Jui-Yi Chiu ,  Nosun Park ,  Je-Hsiung Lan

IPC: H01P7/10 ,  H01P7/06 ,  H01P11/00 ,  H03B5/12

Abstract: In an aspect, an apparatus is disclosed that includes a surface-mounted integrated circuit package housing an active oscillator circuit; an integrated ceramic resonator formed from a ceramic substrate having an upper planar surface receiving the surface-mounted integrated circuit package, the integrated ceramic resonator including a plurality of conductive walls forming a conductive periphery of a ceramic cavity in the ceramic substrate, a conductive rod extending vertically into the ceramic cavity, wherein the conductive rod is isolated from contact with the conductive periphery of the ceramic cavity, a first conductive material extending vertically through the upper planar surface of the ceramic substrate for connecting the conductive periphery of the ceramic cavity to the surface-mounted integrated circuit package housing the active oscillator circuit; and a second conductive material extending through the upper planar surface of the ceramic substrate for connecting the conductive rod to the surface-mounted integrated circuit package.

公开(公告)号：US20230317677A1

公开(公告)日：2023-10-05

申请号：US17657760

申请日：2022-04-04

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jonghae Kim ,  Je-Hsiung Lan ,  Periannan Chidambaram

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/20 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/76898 ,  H01L24/19 ,  H01L25/50 ,  H01L2224/214 ,  H01L2225/06541 ,  H01L2225/06558

Abstract: Three-dimensional (3D) integrated circuit (IC) (3DIC) package employing a redistribution layer (RDL) interposer facilitating semiconductor die (“die”), and related fabrication methods. The 3DIC package includes an RDL interposer that has one or more RDL metallization layers formed adjacent to a first, bottom die(s). A second, top die(s) is stacked on the RDL interposer. The RDL interposer provides an extended die area that the top die can be coupled so that the fabrication process of the 3DIC package is independent die sizes. The bottom die(s) can be singulated and disposed in an RDL metallization layer(s) as part of a reconstituted RDL interposer regardless of whether the top die(s) is greater than or less than the size of the bottom die(s). Also, the RDL interposer being the substrate in which the bottom die(s) is disposed and top die(s) is coupled provides efficient signal routing paths to the top and bottom dies.

公开(公告)号：US11689181B2

公开(公告)日：2023-06-27

申请号：US16884891

申请日：2020-05-27

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Je-Hsiung Lan ,  Ranadeep Dutta ,  Milind Shah ,  Periannan Chidambaram

IPC: H03H9/05 ,  H01L25/04 ,  H03H9/02 ,  H03H9/145 ,  H03H9/64 ,  H10N30/02 ,  H10N30/87 ,  H10N30/88 ,  H03H3/02

CPC classification number: H03H9/058 ,  H01L25/04 ,  H03H3/02 ,  H03H9/02992 ,  H03H9/14544 ,  H03H9/64 ,  H10N30/02 ,  H10N30/875 ,  H10N30/883

Abstract: A package that includes a first filter comprising a first polymer, a substrate cap, a second filter comprising a second polymer frame, at least one interconnect, an encapsulation layer and a plurality of through encapsulation vias. The substrate cap is coupled to the first polymer frame such that a first void is formed between the substrate cap and the first filter. The second polymer frame is coupled to the substrate cap such that a second void is formed between the substrate cap and the second filter. The at least one interconnect is coupled to the first filter and the second filter. The encapsulation layer encapsulates the first filter, the substrate cap, the second filter, and the at least one interconnect. The plurality of through encapsulation vias coupled to the first filter.

公开(公告)号：US11652064B2

公开(公告)日：2023-05-16

申请号：US16706167

申请日：2019-12-06

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Je-Hsiung Lan ,  Ranadeep Dutta

IPC: H01L23/552 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/552 ,  H01L24/08 ,  H01L24/80 ,  H01L25/16 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/3025

Abstract: Improve EM coupling for the wafer-bonding process from a first wafer to a second wafer by a shielding technique. Examples may include building an EM shield implemented by BEOL-stacks/routings, bonding contacts, and TSVs for a closed-loop shielding platform for the integrated device to minimize EM interference from active devices due to eddy currents. The shield may be implemented in the active device layer during a wafer-to-wafer bonding-process that uses two different device layers/wafers, an active device layer/wafer and a passive device layer/wayer. The shield may be designed by the patterned routings for both I/O ports and the GND contacts.

公开(公告)号：US11437367B2

公开(公告)日：2022-09-06

申请号：US16854313

申请日：2020-04-21

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Ranadeep Dutta ,  Jonghae Kim

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/66 ,  H03F3/213

Abstract: A 3D integrated circuit (3D IC) chip is described. The 3D IC chip includes a die having a compound semiconductor high electron mobility transistor (HEMT) active device. The compound semiconductor HEMT active device is composed of compound semiconductor layers on a single crystal, compound semiconductor layer. The 3D IC chip also includes an acoustic device integrated in the single crystal, compound semiconductor layer. The 3D IC chip further includes a passive device integrated in back-end-of-line layers of the die on the single crystal, compound semiconductor layer.

公开(公告)号：US11201127B2

公开(公告)日：2021-12-14

申请号：US16812882

申请日：2020-03-09

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Milind Shah ,  Periannan Chidambaram

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/31 ,  H01L23/64 ,  H01L21/56 ,  H01L23/532

Abstract: A device that includes a first package and a second package coupled to the first package. The first package includes a first integrated device, a first encapsulation layer encapsulating the first integrated device, a plurality of vias traveling through the first encapsulation layer, a first redistribution portion comprising a first plurality of redistribution interconnects, wherein the first redistribution portion is coupled to the first encapsulation layer, and a first plurality of contacts coupled to the first integrated device. The second package includes a passive device, a second encapsulation layer encapsulating the passive device, a second redistribution portion comprising a second plurality of redistribution interconnects, wherein the second redistribution portion is coupled to the passive device and the second encapsulation layer, and a second plurality of contacts coupled to the passive device, wherein the second plurality of contacts is coupled to the first plurality of contacts from the first package.

公开(公告)号：US10903240B2

公开(公告)日：2021-01-26

申请号：US16402713

申请日：2019-05-03

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daniel Daeik Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L27/12 ,  H01L23/498 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/304 ,  H01L27/088 ,  H01L23/66 ,  H01L21/306 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US10693432B2

公开(公告)日：2020-06-23

申请号：US15982655

申请日：2018-05-17

Applicant: QUALCOMM Incorporated

Inventor： Nosun Park ,  Changhan Hobie Yun ,  Jonghae Kim ,  Niranjan Sunil Mudakatte ,  Xiaoju Yu ,  Wei-Chuan Chen

IPC: H03H7/01 ,  H01F27/40 ,  H01L21/56 ,  H01L21/683 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L27/01 ,  H01L49/02 ,  H03H1/00 ,  H03H3/00

Abstract: A three-dimensional (3D) solenoid structure includes a first inductor portion having a first surface and a second surface opposite the first surface. The 3D solenoid structure further includes a first capacitor portion, a first inductor pillar, at least one capacitor pillar, a second inductor portion, a second inductor pillar and a first inductor bonding interface. The first inductor pillar is coupled to the first surface of the first inductor portion. The capacitor pillar(s) is coupled to the first capacitor portion. The second inductor portion includes a first surface and a second surface opposite the first surface. The second inductor pillar is coupled to the first surface of the second inductor portion. The first inductor bonding interface, between the first inductor pillar and the second inductor pillar, couples together the first inductor portion and the second inductor portion.

公开(公告)号：US10187031B2

公开(公告)日：2019-01-22

申请号：US15151351

申请日：2016-05-10

Applicant: QUALCOMM Incorporated

Inventor： Yunfei Ma ,  Chengjie Zuo ,  David Francis Berdy ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H03H7/38 ,  H03H7/40 ,  H04B1/04

Abstract: A tunable matching network is disclosed. In a particular example, the matching network includes at least one first inductor in a signal path of the matching network. The matching network includes at least one second inductor outside of the signal path. The matching network includes one or more switches coupled to the at least one second inductor. The one or more switches are configured to selectively enable mutual coupling of the at least one first inductor and the at least one second inductor.