Multilevel imprint lithography
    4.
    发明申请
    Multilevel imprint lithography 失效
    多层压印光刻

    公开(公告)号:US20100112809A1

    公开(公告)日:2010-05-06

    申请号:US11636264

    申请日:2006-12-07

    IPC分类号: H01L21/768

    摘要: A mold with a protruding pattern is provided that is pressed into a thin polymer film via an imprinting process. Controlled connections between nanowires and microwires and other lithographically-made elements of electronic circuitry are provided. An imprint stamp is configured to form arrays of approximately parallel nanowires which have (1) micro dimensions in the X direction, (2) nano dimensions and nano spacing in the Y direction, and three or more distinct heights in the Z direction. The stamp thus formed can be used to connect specific individual nanowires to specific microscopic regions of microscopic wires or pads. The protruding pattern in the mold creates recesses in the thin polymer film, so the polymer layer acquires the reverse of the pattern on the mold. After the mold is removed, the film is processed such that the polymer pattern can be transferred on a metal/semiconductor pattern on the substrate.

    摘要翻译: 提供具有突出图案的模具,其通过压印过程被压入薄聚合物膜。 提供了纳米线和微丝之间的控制连接以及电子电路的其它光刻元件。 打印印记被配置成形成大致平行的纳米线的阵列,其具有(1)X方向上的微尺寸,(2)在Y方向上的纳米尺寸和纳米间距,以及Z方向上的三个或更多个不同的高度。 如此形成的印章可以用于将特定的单个纳米线连接到微细线或垫的特定微观区域。 模具中的突出图案在薄聚合物膜中产生凹陷,因此聚合物层获得模具上图案的相反。 在除去模具之后,处理膜,使得聚合物图案可以在基底上的金属/半导体图案上转印。

    Multilevel imprint lithography
    5.
    发明授权
    Multilevel imprint lithography 有权
    多层压印光刻

    公开(公告)号:US07256435B1

    公开(公告)日:2007-08-14

    申请号:US10453329

    申请日:2003-06-02

    IPC分类号: H01L27/10

    摘要: A mold with a protruding pattern is provided that is pressed into a thin polymer film via an imprinting process. Controlled connections between nanowires and microwires and other lithographically-made elements of electronic circuitry are provided. An imprint stamp is configured to form arrays of approximately parallel nanowires which have (1) micro dimensions in the X direction, (2) nano dimensions and nano spacing in the Y direction, and three or more distinct heights in the Z direction. The stamp thus formed can be used to connect specific individual nanowires to specific microscopic regions of microscopic wires or pads. The protruding pattern in the mold creates recesses in the thin polymer film, so the polymer layer acquires the reverse of the pattern on the mold. After the mold is removed, the film is processed such that the polymer pattern can be transferred on a metal/semiconductor pattern on the substrate.

    摘要翻译: 提供具有突出图案的模具,其通过压印过程被压入薄聚合物膜。 提供了纳米线和微丝之间的控制连接以及电子电路的其它光刻元件。 打印印记被配置成形成大致平行的纳米线的阵列,其具有(1)X方向上的微尺寸,(2)在Y方向上的纳米尺寸和纳米间距,以及Z方向上的三个或更多个不同的高度。 如此形成的印章可以用于将特定的单个纳米线连接到微细线或垫的特定微观区域。 模具中的突出图案在薄聚合物膜中产生凹陷,因此聚合物层获得模具上图案的相反。 在除去模具之后,处理膜,使得聚合物图案可以在基底上的金属/半导体图案上转印。

    Polymer solution for nanoimprint lithography to reduce imprint temperature and pressure
    8.
    发明授权
    Polymer solution for nanoimprint lithography to reduce imprint temperature and pressure 失效
    用于纳米压印光刻的聚合物溶液,以减少压印温度和压力

    公开(公告)号:US07750059B2

    公开(公告)日:2010-07-06

    申请号:US10313596

    申请日:2002-12-04

    IPC分类号: B29C35/08

    摘要: A method of forming features on substrates by imprinting is provided. The method comprises: (a) forming a polymer solution comprising at least one polymer dissolved in at least one polymerizable monomer; and (b) depositing the polymer solution on a substrate to form a liquid film thereon; and then either: (c) curing the liquid film by causing the monomer(s) to polymerize and optionally cross-linking the polymer(s) to thereby form a polymer film, the polymer film having a glass transition temperature (Tg); and imprinting the polymer film with a mold having a desired pattern to form a corresponding negative pattern in the polymer film, or (d) imprinting the liquid film with the mold and curing it to form the polymer film. The temperature of imprinting is as little as 10° C. above the Tg, or even less if the film is in the liquid state. The pressure of the imprinting can be within the range of 100 to 500 psi.

    摘要翻译: 提供了通过压印在基板上形成特征的方法。 该方法包括:(a)形成包含至少一种溶解在至少一种可聚合单体中的聚合物的聚合物溶液; 和(b)将聚合物溶液沉积在基底上以在其上形成液膜; 然后:(c)通过使单体聚合并任选地交联聚合物从而形成聚合物膜来固化液膜,所述聚合物膜具有玻璃化转变温度(Tg); 并用具有所需图案的模具印刷聚合物膜,以在聚合物膜中形成相应的负图案,或(d)用模具印刷液膜并固化以形成聚合物膜。 压印温度比Tg高出10℃,或者如果薄膜处于液体状态,则其温度更低。 压印的压力可以在100-500psi的范围内。

    Electric device having nanoscale wires and gaps
    9.
    发明授权
    Electric device having nanoscale wires and gaps 失效
    具有纳米线和间隙的电器件

    公开(公告)号:US07087946B2

    公开(公告)日:2006-08-08

    申请号:US10697589

    申请日:2003-10-30

    摘要: A method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has an asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.

    摘要翻译: 一种用于形成第一组合物的第一和第二线性结构的方法,所述第一和第二线性结构垂直相交,在所述结构相交点处存在间隙。 线性结构构造在具有第一组成的可蚀刻晶体层上。 在该层上生长第二组合物的第一和第二自对准纳米线,并用作蚀刻该层的掩模。 自对准纳米线由相对于晶体层具有不对称晶格失配的材料构成。 该间隙足够小以允许一个结构用作晶体管的栅极,而另一个则形成晶体管的源极和漏极。 间隙可以用电可切换材料填充,从而将晶体管转换成存储单元。

    Configurable nanoscale crossbar electronic circuits made by electrochemical reaction
    10.
    发明授权
    Configurable nanoscale crossbar electronic circuits made by electrochemical reaction 有权
    通过电化学反应制造的可配置的纳米级横梁电子电路

    公开(公告)号:US06891744B2

    公开(公告)日:2005-05-10

    申请号:US10289703

    申请日:2002-11-06

    摘要: Configurable electronic circuits comprise arrays of cross-points of one layer of metal/semiconductive nanoscale lines crossed by a second layer of metal/semiconductive nanoscale lines, with a configurable layer between the lines. Methods are provided for altering the thickness and/or resistance of the configurable layer by oxidation or reduction methods, employing a solid material as the configurable layer. Specifically a method is provided for configuring nanoscale devices in a crossbar array of configurable devices comprising arrays of cross-points of a first layer of nanoscale lines comprising a first metal or a first semiconductor material crossed by a second layer of nanoscale lines comprising a second metal or a second semiconductor material. The method comprises: (a) forming the first layer on a substrate; (b) forming a solid phase of a configurable material on the first layer at least in areas where the second layer is to cross the first layer; (c) forming the second layer on the configurable material, over the first layer; and (d) changing a property of the configurable material to thereby configure the nanoscale devices.

    摘要翻译: 可配置电子电路包括由第二层金属/半导体纳米级线交叉的一层金属/半导体纳米级线的交叉点阵列,其中线之间具有可配置层。 提供了通过使用固体材料作为可配置层的氧化或还原方法来改变可配置层的厚度和/或电阻的方法。 具体地,提供一种用于在可配置设备的交叉开关阵列中配置纳米级器件的方法,其包括第一纳米级线层的交点的阵列,其包括第一金属或第一半导体材料,所述第一金属或第一半导体材料由第二纳米级线交叉,所述第二金属或第二半导体材料包括第二金属 或第二半导体材料。 该方法包括:(a)在衬底上形成第一层; (b)至少在所述第二层与所述第一层交叉的区域中,在所述第一层上形成可配置材料的固相; (c)在所述可配置材料上形成在所述第一层上的所述第二层; 和(d)改变可配置材料的特性,从而配置纳米级器件。