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    Polymer solution for nanoimprint lithography to reduce imprint temperature and pressure
    1.
    发明授权
    Polymer solution for nanoimprint lithography to reduce imprint temperature and pressure 失效
    用于纳米压印光刻的聚合物溶液，以减少压印温度和压力

    公开(公告)号：US07750059B2

    公开(公告)日：2010-07-06

    申请号：US10313596

    申请日：2002-12-04

    申请人： Gun Young Jung ,  Sivapackia Ganapathiappan ,  Yong Chen ,  R. Stanley Williams

    发明人： Gun Young Jung ,  Sivapackia Ganapathiappan ,  Yong Chen ,  R. Stanley Williams

    IPC分类号： B29C35/08

    CPC分类号： B29C43/003 ,  B29C35/0888 ,  B29C59/022 ,  B29C2035/0827 ,  B29C2043/025 ,  B29C2059/023 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/033

    摘要： A method of forming features on substrates by imprinting is provided. The method comprises: (a) forming a polymer solution comprising at least one polymer dissolved in at least one polymerizable monomer; and (b) depositing the polymer solution on a substrate to form a liquid film thereon; and then either: (c) curing the liquid film by causing the monomer(s) to polymerize and optionally cross-linking the polymer(s) to thereby form a polymer film, the polymer film having a glass transition temperature (Tg); and imprinting the polymer film with a mold having a desired pattern to form a corresponding negative pattern in the polymer film, or (d) imprinting the liquid film with the mold and curing it to form the polymer film. The temperature of imprinting is as little as 10° C. above the Tg, or even less if the film is in the liquid state. The pressure of the imprinting can be within the range of 100 to 500 psi.

    摘要翻译： 提供了通过压印在基板上形成特征的方法。 该方法包括：（a）形成包含至少一种溶解在至少一种可聚合单体中的聚合物的聚合物溶液; 和（b）将聚合物溶液沉积在基底上以在其上形成液膜; 然后：（c）通过使单体聚合并任选地交联聚合物从而形成聚合物膜来固化液膜，所述聚合物膜具有玻璃化转变温度（Tg）; 并用具有所需图案的模具印刷聚合物膜，以在聚合物膜中形成相应的负图案，或（d）用模具印刷液膜并固化以形成聚合物膜。 压印温度比Tg高出10℃，或者如果薄膜处于液体状态，则其温度更低。 压印的压力可以在100-500psi的范围内。

    Electric device having nanoscale wires and gaps
    2.
    发明授权
    Electric device having nanoscale wires and gaps 失效
    具有纳米线和间隙的电器件

    公开(公告)号：US07087946B2

    公开(公告)日：2006-08-08

    申请号：US10697589

    申请日：2003-10-30

    申请人： Yong Chen ,  R. Stanley Williams

    发明人： Yong Chen ,  R. Stanley Williams

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/3081 ,  B82Y10/00 ,  G11C2213/81 ,  H01L21/3083 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42312 ,  H01L29/66439 ,  Y10S438/945 ,  Y10S438/962 ,  Y10S977/888

    摘要： A method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has an asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.

    摘要翻译： 一种用于形成第一组合物的第一和第二线性结构的方法，所述第一和第二线性结构垂直相交，在所述结构相交点处存在间隙。 线性结构构造在具有第一组成的可蚀刻晶体层上。 在该层上生长第二组合物的第一和第二自对准纳米线，并用作蚀刻该层的掩模。 自对准纳米线由相对于晶体层具有不对称晶格失配的材料构成。 该间隙足够小以允许一个结构用作晶体管的栅极，而另一个则形成晶体管的源极和漏极。 间隙可以用电可切换材料填充，从而将晶体管转换成存储单元。

    Configurable nanoscale crossbar electronic circuits made by electrochemical reaction
    3.
    发明授权
    Configurable nanoscale crossbar electronic circuits made by electrochemical reaction 有权
    通过电化学反应制造的可配置的纳米级横梁电子电路

    公开(公告)号：US06891744B2

    公开(公告)日：2005-05-10

    申请号：US10289703

    申请日：2002-11-06

    申请人： Yong Chen ,  R. Stanley Williams

    发明人： Yong Chen ,  R. Stanley Williams

    IPC分类号： G11C13/02 ,  G11C13/00 ,  H01L21/31 ,  H01L21/44

    CPC分类号： G11C13/0009 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/34 ,  G11C2213/77 ,  G11C2213/81 ,  Y10S438/957 ,  Y10S977/936

    摘要： Configurable electronic circuits comprise arrays of cross-points of one layer of metal/semiconductive nanoscale lines crossed by a second layer of metal/semiconductive nanoscale lines, with a configurable layer between the lines. Methods are provided for altering the thickness and/or resistance of the configurable layer by oxidation or reduction methods, employing a solid material as the configurable layer. Specifically a method is provided for configuring nanoscale devices in a crossbar array of configurable devices comprising arrays of cross-points of a first layer of nanoscale lines comprising a first metal or a first semiconductor material crossed by a second layer of nanoscale lines comprising a second metal or a second semiconductor material. The method comprises: (a) forming the first layer on a substrate; (b) forming a solid phase of a configurable material on the first layer at least in areas where the second layer is to cross the first layer; (c) forming the second layer on the configurable material, over the first layer; and (d) changing a property of the configurable material to thereby configure the nanoscale devices.

    摘要翻译： 可配置电子电路包括由第二层金属/半导体纳米级线交叉的一层金属/半导体纳米级线的交叉点阵列，其中线之间具有可配置层。 提供了通过使用固体材料作为可配置层的氧化或还原方法来改变可配置层的厚度和/或电阻的方法。 具体地，提供一种用于在可配置设备的交叉开关阵列中配置纳米级器件的方法，其包括第一纳米级线层的交点的阵列，其包括第一金属或第一半导体材料，所述第一金属或第一半导体材料由第二纳米级线交叉，所述第二金属或第二半导体材料包括第二金属 或第二半导体材料。 该方法包括：（a）在衬底上形成第一层; （b）至少在所述第二层与所述第一层交叉的区域中，在所述第一层上形成可配置材料的固相; （c）在所述可配置材料上形成在所述第一层上的所述第二层; 和（d）改变可配置材料的特性，从而配置纳米级器件。

    Nanowire device with (111) vertical sidewalls and method of fabrication
    5.
    发明授权
    Nanowire device with (111) vertical sidewalls and method of fabrication 失效
    具有（111）垂直侧壁的纳米线器件和制造方法

    公开(公告)号：US07692179B2

    公开(公告)日：2010-04-06

    申请号：US10888628

    申请日：2004-07-09

    申请人： M. Saif Islam ,  Yong Chen ,  Shih-Yuan Wang ,  R. Stanley Williams

    发明人： M. Saif Islam ,  Yong Chen ,  Shih-Yuan Wang ,  R. Stanley Williams

    IPC分类号： H01L29/06

    CPC分类号： H01L27/1203 ,  B82Y10/00 ,  G11C2213/81 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/861

    摘要： A nano-scale device and method of fabrication provide a nanowire having (111) vertical sidewalls. The nano-scale device includes a semiconductor-on-insulator substrate polished in a [110] direction, the nanowire, and an electrical contact at opposite ends of the nanowire. The method includes wet etching a semiconductor layer of the semiconductor-on-insulator substrate to form the nanowire extending between a pair of islands in the semiconductor layer. The method further includes depositing an electrically conductive material on the pair of islands to form the electrical contacts. A nano-pn diode includes the nanowire as a first nano-electrode, a pn-junction vertically stacked on the nanowire, and a second nano-electrode on a (110) horizontal planar end of the pn-junction. The nano-pn diode may be fabricated in an array of the diodes on the semiconductor-on-insulator substrate.

    摘要翻译： 纳米级器件和制造方法提供具有（111）垂直侧壁的纳米线。 纳米级器件包括在[110]方向上抛光的绝缘体上半导体衬底，纳米线和在纳米线的相对端的电接触。 该方法包括湿式蚀刻绝缘体上半导体衬底的半导体层，以形成在半导体层中的一对岛之间延伸的纳米线。 该方法还包括在一对岛上沉积导电材料以形成电触头。 纳米pn二极管包括纳米线作为第一纳米电极，垂直堆叠在纳米线上的pn结，以及在pn结的（110）水平平面端上的第二纳米电极。 可以在绝缘体上半导体衬底上的二极管的阵列中制造纳米pn二极管。

    Method for fabricating a nano-imprinting mold
    9.
    发明授权
    Method for fabricating a nano-imprinting mold 失效
    用于压印光刻及其制造的装置

    公开(公告)号：US07368395B2

    公开(公告)日：2008-05-06

    申请号：US11601084

    申请日：2006-11-16

    申请人： M. Saif Islam ,  Gun Young Jung ,  Yong Chen ,  R. Stanley Williams

    发明人： M. Saif Islam ,  Gun Young Jung ,  Yong Chen ,  R. Stanley Williams

    IPC分类号： H01L21/461

    CPC分类号： H01L21/76838 ,  H01L21/0337

    摘要： An imprinting apparatus and method of fabrication provide a mold having a pattern for imprinting. The apparatus includes a semiconductor substrate polished in a [110] direction. The semiconductor substrate has a (110) horizontal planar surface and vertical sidewalls of a wet chemical etched trench. The sidewalls are aligned with and therefore are (111) vertical lattice planes of the semiconductor substrate. The semiconductor substrate includes a plurality of vertical structures between the sidewalls, wherein the vertical structures may be nano-scale spaced apart. The method includes wet etching a trench with spaced apart (111) vertical sidewalls in an exposed portion of the (110) horizontal surface of the semiconductor substrate along (111) vertical lattice planes. A chemical etching solution is used that etches the (111) vertical lattice planes slower than the (110) horizontal lattice plane. The method further includes forming the imprinting mold.

    摘要翻译： 压印装置和制造方法提供具有用于压印的图案的模具。 该装置包括沿[110]方向抛光的半导体衬底。 半导体衬底具有（110）水平平面和湿化学蚀刻沟槽的垂直侧壁。 侧壁与半导体衬底对准并且因此是（111）垂直的晶格面。 半导体衬底包括在侧壁之间的多个垂直结构，其中垂直结构可以是纳米级隔开的。 该方法包括在（111）垂直晶格面的半导体衬底的（110）水平表面的暴露部分中湿式蚀刻具有间隔开（111）垂直侧壁的沟槽。 使用蚀刻比（110）水平晶格面慢的（111）垂直晶格面的化学蚀刻溶液。 该方法还包括形成压印模具。