公开(公告)号：US20180076115A1

公开(公告)日：2018-03-15

申请号：US15818684

申请日：2017-11-20

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Tsukasa MATSUSHITA ,  Atsushi NISHIKIZAWA

IPC: H01L23/495 ,  H01L23/29 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4828 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49582 ,  H01L24/43 ,  H01L24/46 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2224/85 ,  H01L2224/83

Abstract: An improvement is achieved in the reliability of a semiconductor device. After a resin sealing portion is formed to seal a die pad, a semiconductor chip mounted over the die pad, a plurality of leads, and a plurality of wires electrically connecting a plurality of pad electrodes of the semiconductor chip with the leads, the resin sealing portion and the leads are cut with a rotary blade to manufacture the semiconductor device. In the semiconductor device, at least a portion of each of first and second leads is exposed from a lower surface of the sealing portion. End surfaces of the first and second leads as the respective cut surfaces thereof are exposed from each of side surfaces of the sealing portion as the cut surfaces of the resin sealing portion. The distance between a lower side of the end surface of the first lead and an upper surface of the sealing portion is smaller than the distance between an upper side of the end surface of the second lead adjacent thereto and the upper surface of the sealing portion.

公开(公告)号：US20170309550A1

公开(公告)日：2017-10-26

申请号：US15462864

申请日：2017-03-19

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Tsukasa MATSUSHITA ,  Atsushi NISHIKIZAWA

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4828 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49582 ,  H01L24/43 ,  H01L24/46 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2224/85 ,  H01L2224/83

Abstract: An improvement is achieved in the reliability of a semiconductor device. After a resin sealing portion is formed to seal a die pad, a semiconductor chip mounted over the die pad, a plurality of leads, and a plurality of wires electrically connecting a plurality of pad electrodes of the semiconductor chip with the leads, the resin sealing portion and the leads are cut with a rotary blade to manufacture the semiconductor device. In the semiconductor device, at least a portion of each of first and second leads is exposed from a lower surface of the sealing portion. End surfaces of the first and second leads as the respective cut surfaces thereof are exposed from each of side surfaces of the sealing portion as the cut surfaces of the resin sealing portion. The distance between a lower side of the end surface of the first lead and an upper surface of the sealing portion is smaller than the distance between an upper side of the end surface of the second lead adjacent thereto and the upper surface of the sealing portion.

公开(公告)号：US20180315685A1

公开(公告)日：2018-11-01

申请号：US16020353

申请日：2018-06-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi NISHIKIZAWA ,  Yuichi YATO ,  Hiroi OKA ,  Tadatoshi DANNO ,  Hiroyuki NAKAMURA

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.

公开(公告)号：US20170221800A1

公开(公告)日：2017-08-03

申请号：US15515297

申请日：2015-03-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi NISHIKIZAWA ,  Yuichi YATO ,  Hiroi OKA ,  Tadatoshi DANNO ,  Hiroyuki NAKAMURA

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.

公开(公告)号：US20170077069A1

公开(公告)日：2017-03-16

申请号：US15211421

申请日：2016-07-15

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Atsushi NISHIKIZAWA

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L23/29 ,  H01L23/495 ,  H01L21/48 ,  H01L23/047 ,  H01L23/498

CPC classification number: H01L24/73 ,  H01L21/4853 ,  H01L23/047 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49827 ,  H01L23/49844 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/92247 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/181 ,  H05K1/0206 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.

Abstract translation: 半导体器件的可靠性得到改善。 在管芯焊盘上安装第一和第二半导体芯片。 第一和第二半导体芯片和芯片焊盘的一部分被密封在密封部分中。 第一半导体芯片包括功率晶体管。 第二半导体芯片控制第一半导体芯片。 安装第一半导体芯片的芯片焊盘部分的厚度小于安装第二半导体芯片的芯片焊盘部分的厚度。

公开(公告)号：US20160093557A1

公开(公告)日：2016-03-31

申请号：US14871769

申请日：2015-09-30

Applicant: Renesas Electronics Corporation

Inventor： Atsushi NISHIKIZAWA ,  Tadatoshi DANNO ,  Hiroyuki NAKAMURA ,  Osamu SOMA ,  Akira UEMURA

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/58 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/585 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/33505 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.

Abstract translation: 半导体器件包括第一和第二半导体芯片，多个引线，多个引线和密封这些部件的密封体。 电连接到第一和第二电极焊盘的第一焊盘电极，第二焊盘电极和内部布线形成在第一半导体芯片的主表面上。 第二半导体芯片的第三焊盘电极经由第一导线电连接到第一半导体芯片的第一电极焊盘，第一半导体芯片的第二电极焊盘经由第二导线电连接到第一引线。 第一引线和第一半导体芯片之间的距离小于第一引线和第二半导体芯片之间的距离。 第一电极焊盘，第二电极焊盘和内部布线不连接到形成在第一半导体芯片中的任何电路。

公开(公告)号：US20180182692A1

公开(公告)日：2018-06-28

申请号：US15826815

申请日：2017-11-30

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Atsushi NISHIKIZAWA ,  Hiroyuki NAKAMURA

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49503 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49551 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/562 ,  H01L2224/05554 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H02P27/06 ,  H01L2924/00012

Abstract: An improvement is achieved in the reliability of a semiconductor device. A SIP includes an analog chip, a microcomputer chip having a main surface smaller in area than a main surface of the analog chip, a die pad over which the analog chip and the microcomputer chip are mounted, and a plurality of leads arranged so as to surround the die pad. The SIP further includes a plurality of suspension leads formed integrally with the die pad, a plurality of wires electrically coupling electrodes of the analog chip to the leads and electrically coupling the microcomputer chip to the leads, and a sealing body sealing therein the analog chip and the microcomputer chip. Each of first and second curved portions of the die pad has a radius of curvature larger than a radius of curvature of a third curved portion of the die pad.

公开(公告)号：US20180151479A1

公开(公告)日：2018-05-31

申请号：US15715544

申请日：2017-09-26

Applicant: Renesas Electronics Corporation

Inventor： Atsushi NISHIKIZAWA ,  Tadatoshi DANNO

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: In order to improve reliability of a semiconductor device, the semiconductor device includes a semiconductor chip, a die pad, a plurality of leads, and a sealing portion. The die pad and the leads are made of a metal material mainly containing copper. A plating layer is formed on a top surface of the die pad. The plating layer is formed by a silver plating layer, a gold plating layer, or a platinum plating layer. The semiconductor chip is mounted on the plating layer on the top surface of the die pad via a bonding material. The plating layer is covered by the bonding material not to be in contact with the sealing portion.

公开(公告)号：US20170301643A1

公开(公告)日：2017-10-19

申请号：US15641985

申请日：2017-07-05

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Atsushi NISHIKIZAWA

IPC: H01L23/00 ,  H01L23/047 ,  H01L23/367 ,  H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L24/73 ,  H01L21/4853 ,  H01L23/047 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49827 ,  H01L23/49844 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/92247 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/181 ,  H05K1/0206 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.