公开(公告)号：US09583502B2

公开(公告)日：2017-02-28

申请号：US14874295

申请日：2015-10-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi Nishikizawa ,  Takuro Homma ,  Hiraku Chakihara ,  Mitsuhiro Noguchi

IPC: H01L21/70 ,  H01L21/8246 ,  H01L21/28 ,  H01L29/51 ,  H01L29/45 ,  H01L29/423 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/265 ,  H01L21/283 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/49

CPC classification number: H01L27/11568 ,  H01L21/265 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.

Abstract translation: 在半导体衬底的主表面上形成第一膜之后，对第一膜进行构图，从而形成用于非易失性存储器，虚拟栅电极和第一膜图案的控制栅电极。 随后，形成用于与控制栅电极相邻的非易失性存储器的存储栅电极。 然后，对第一胶片图案进行图案化，从而形成栅电极和伪栅电极。

公开(公告)号：US20160027794A1

公开(公告)日：2016-01-28

申请号：US14874295

申请日：2015-10-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi Nishikizawa ,  Takuro Homma ,  Hiraku Chakihara ,  Mitsuhiro Noguchi

IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/311 ,  H01L21/265 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L21/32 ,  H01L29/66 ,  H01L29/423 ,  H01L21/283 ,  H01L21/768

CPC classification number: H01L27/11568 ,  H01L21/265 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.

Abstract translation: 在半导体衬底的主表面上形成第一膜之后，对第一膜进行构图，从而形成用于非易失性存储器，虚拟栅电极和第一膜图案的控制栅电极。 随后，形成用于与控制栅电极相邻的非易失性存储器的存储栅电极。 然后，对第一胶片图案进行图案化，从而形成栅电极和伪栅电极。

公开(公告)号：US09171727B2

公开(公告)日：2015-10-27

申请号：US14146054

申请日：2014-01-02

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi Nishikizawa ,  Takuro Homma ,  Hiraku Chakihara ,  Mitsuhiro Noguchi

IPC: H01L29/792 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/265 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.

Abstract translation: 在半导体衬底的主表面上形成第一膜之后，对第一膜进行构图，从而形成用于非易失性存储器，虚拟栅电极和第一膜图案的控制栅电极。 随后，形成用于与控制栅电极相邻的非易失性存储器的存储栅电极。 然后，对第一胶片图案进行图案化，从而形成栅电极和伪栅电极。