公开(公告)号：US09536821B2

公开(公告)日：2017-01-03

申请号：US14666602

申请日：2015-03-24

Applicant: Renesas Electronics Corporation

Inventor： Takuro Homma ,  Katsuhiko Hotta ,  Takashi Moriyama

IPC: H01L23/48 ,  H01L23/50 ,  H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L23/482

CPC classification number: H01L23/50 ,  H01L22/32 ,  H01L23/3192 ,  H01L23/4827 ,  H01L24/03 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48624 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

Abstract translation: 在制造LSI或半导体集成电路器件时，组装器件（如树脂密封步骤）的步骤通常在高温（例如85〜130℃）的环境中进行电压施加试验， 高湿度（例如约80％RH）。 已经发现，在测试中施加正电压的铝基焊盘的上表面边缘部分处，从上膜分离氮化钛抗反射膜和在氮化钛膜中产生裂纹 通过由于通过密封树脂等的水分引起的电化学反应，以产生氮化钛膜的氧化和膨胀。 这些问题通过在铝基焊盘的周边区域以环或狭缝形状移除焊盘上的氮化钛膜来解决。

公开(公告)号：US09583502B2

公开(公告)日：2017-02-28

申请号：US14874295

申请日：2015-10-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi Nishikizawa ,  Takuro Homma ,  Hiraku Chakihara ,  Mitsuhiro Noguchi

IPC: H01L21/70 ,  H01L21/8246 ,  H01L21/28 ,  H01L29/51 ,  H01L29/45 ,  H01L29/423 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/265 ,  H01L21/283 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/49

CPC classification number: H01L27/11568 ,  H01L21/265 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.

Abstract translation: 在半导体衬底的主表面上形成第一膜之后，对第一膜进行构图，从而形成用于非易失性存储器，虚拟栅电极和第一膜图案的控制栅电极。 随后，形成用于与控制栅电极相邻的非易失性存储器的存储栅电极。 然后，对第一胶片图案进行图案化，从而形成栅电极和伪栅电极。

公开(公告)号：US20160027794A1

公开(公告)日：2016-01-28

申请号：US14874295

申请日：2015-10-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi Nishikizawa ,  Takuro Homma ,  Hiraku Chakihara ,  Mitsuhiro Noguchi

IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/311 ,  H01L21/265 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L21/32 ,  H01L29/66 ,  H01L29/423 ,  H01L21/283 ,  H01L21/768

CPC classification number: H01L27/11568 ,  H01L21/265 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.

Abstract translation: 在半导体衬底的主表面上形成第一膜之后，对第一膜进行构图，从而形成用于非易失性存储器，虚拟栅电极和第一膜图案的控制栅电极。 随后，形成用于与控制栅电极相邻的非易失性存储器的存储栅电极。 然后，对第一胶片图案进行图案化，从而形成栅电极和伪栅电极。

公开(公告)号：US09171727B2

公开(公告)日：2015-10-27

申请号：US14146054

申请日：2014-01-02

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi Nishikizawa ,  Takuro Homma ,  Hiraku Chakihara ,  Mitsuhiro Noguchi

IPC: H01L29/792 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/265 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.

Abstract translation: 在半导体衬底的主表面上形成第一膜之后，对第一膜进行构图，从而形成用于非易失性存储器，虚拟栅电极和第一膜图案的控制栅电极。 随后，形成用于与控制栅电极相邻的非易失性存储器的存储栅电极。 然后，对第一胶片图案进行图案化，从而形成栅电极和伪栅电极。