公开(公告)号：US09475692B2

公开(公告)日：2016-10-25

申请号：US14805774

申请日：2015-07-22

Applicant: RF Micro Devices, Inc.

Inventor： Julio C. Costa ,  Michael Carroll ,  Jonathan Hale Hammond

IPC: B81B7/00 ,  H01H1/00

CPC classification number: B81B7/0064 ,  H01H1/0036

Abstract: The present disclosure relates to radio frequency (RF) microelectromechanical system (MEMS) device packaging, and specifically to reducing harmonic distortion caused by such packaging. In one embodiment, a die is provided that employs a gold-doped silicon substrate, wherein at least one RF MEMS device is disposed on the gold-doped silicon substrate. By employing the gold-doped silicon substrate, the packaging can achieve an exceptionally high resistivity without any additional expensive components, wherein the high resistivity has an associated low carrier lifetime. Notably, the low carrier lifetime corresponds to reduced harmonic distortion generated by the gold-doped silicon substrate, even when operating at high power. Thus, the gold-doped silicon substrate provides a less expensive packaging in which to place RF MEMS devices, wherein the packaging is capable of operating at high power with reduced harmonic distortion.

Abstract translation: 本公开涉及射频（RF）微机电系统（MEMS）设备封装，并且具体涉及减少由这种封装引起的谐波失真。 在一个实施例中，提供一种使用金掺杂硅衬底的管芯，其中至少一个RF MEMS器件设置在掺金硅衬底上。 通过采用金掺杂硅衬底，封装可以实现非常高的电阻率，而没有任何额外的昂贵的组件，其中高电阻率具有相关联的低载流子寿命。 值得注意的是，低载流子寿命对应于由金掺杂硅衬底产生的减少的谐波失真，即使在高功率下操作。 因此，金掺杂硅衬底提供了一种较便宜的封装，其中放置RF MEMS器件，其中封装能够以较低功率运行并减少谐波失真。

公开(公告)号：US20140252567A1

公开(公告)日：2014-09-11

申请号：US14261029

申请日：2014-04-24

Applicant: RF Micro Devices, Inc.

Inventor： Michael Carroll ,  Julio Costa ,  Daniel Charles Kerr ,  Don Willis ,  Elizabeth Glass

IPC: H01L29/02 ,  H01L21/02

CPC classification number: H01L21/0237 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/485 ,  H01L29/0657 ,  H01L29/78606 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/13

Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure attached to a wafer handle having at least one aperture that extends through the wafer handle to an exposed portion of the semiconductor stack structure. A thermally conductive and electrically resistive polymer substantially fills the at least one aperture and contacts the exposed portion of the semiconductor stack structure. One method for manufacturing the semiconductor device includes forming patterned apertures in the wafer handle to expose a portion of the semiconductor stack structure. The patterned apertures may or may not be aligned with sections of RF circuitry making up the semiconductor stack structure. A following step includes contacting the exposed portion of the semiconductor stack structure with a polymer and substantially filling the patterned apertures with the polymer, wherein the polymer is thermally conductive and electrically resistive.

Abstract translation: 公开了一种半导体器件及其制造方法。 半导体器件包括附接到晶片把手的半导体堆叠结构，其具有至少一个孔，其延伸穿过晶片把手到达半导体堆叠结构的暴露部分。 导热和电阻聚合物基本上填充至少一个孔并接触半导体堆叠结构的暴露部分。 用于制造半导体器件的一种方法包括在晶片手柄中形成图案化孔以暴露半导体堆叠结构的一部分。 图案化的孔可以或可以不与构成半导体堆叠结构的RF电路的部分对准。 接下来的步骤包括使半导体堆叠结构的暴露部分与聚合物接触，并且用聚合物基本上填充图案化的孔，其中聚合物是导热的并具有电阻性。

公开(公告)号：US09806192B2

公开(公告)日：2017-10-31

申请号：US15133669

申请日：2016-04-20

Applicant: RF Micro Devices, Inc.

Inventor： Philip W. Mason ,  Michael Carroll ,  Julio C. Costa ,  Jan Edward Vandemeer ,  Daniel Charles Kerr

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L23/66

CPC classification number: H01L29/7838 ,  H01L23/66 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78654

Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate structure with a buried dielectric layer for radio frequency (RF) complementary metal-oxide semiconductor (CMOS) switch fabrications. The buried dielectric layer suppresses back-gate transistors in the RF CMOS switches fabricated on the SOI substrate structure. The SOI substrate structure includes a silicon handle layer, a silicon oxide layer over the silicon handle layer, a buried dielectric layer over the silicon oxide layer, and a silicon epitaxy layer directly over the buried dielectric layer.

公开(公告)号：US20160380101A1

公开(公告)日：2016-12-29

申请号：US15133669

申请日：2016-04-20

Applicant: RF Micro Devices, Inc.

Inventor： Philip W. Mason ,  Michael Carroll ,  Julio C. Costa ,  Jan Edward Vandemeer ,  Daniel Charles Kerr

IPC: H01L29/78 ,  H01L27/12 ,  H01L23/66 ,  H01L27/092

CPC classification number: H01L29/7838 ,  H01L23/66 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78654

Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate structure with a buried dielectric layer for radio frequency (RF) complementary metal-oxide semiconductor (CMOS) switch fabrications. The buried dielectric layer suppresses back-gate transistors in the RF CMOS switches fabricated on the SOI substrate structure. The SOI substrate structure includes a silicon handle layer, a silicon oxide layer over the silicon handle layer, a buried dielectric layer over the silicon oxide layer, and a silicon epitaxy layer directly over the buried dielectric layer.

Abstract translation: 本公开涉及具有用于射频（RF）互补金属氧化物半导体（CMOS）开关制造的掩埋介电层的绝缘体上硅（SOI）衬底结构。 掩埋介质层抑制在SOI衬底结构上制造的RF CMOS开关中的背栅晶体管。 SOI衬底结构包括硅手柄层，硅手柄层上的氧化硅层，氧化硅层上的掩埋电介质层，以及直接在掩埋电介质层上的硅外延层。

公开(公告)号：US20140306324A1

公开(公告)日：2014-10-16

申请号：US14315765

申请日：2014-06-26

Applicant: RF Micro Devices, Inc.

Inventor： Julio Costa ,  Michael Carroll ,  Daniel Charles Kerr ,  Don Willis ,  Elizabeth Glass

IPC: H01L23/373

CPC classification number: H01L23/3737 ,  H01L21/565 ,  H01L21/6836 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/367 ,  H01L24/13 ,  H01L2221/6834 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure having a first surface and a second surface. A polymer substrate having a high thermal conductivity and a high electrical resistivity is disposed onto the first surface of the semiconductor stack structure. One method includes providing the semiconductor stack structure with the first surface in direct contact with a wafer handle. A next step involves removing the wafer handle to expose the first surface of the semiconductor stack structure. A following step includes disposing a polymer substrate having high thermal conductivity and high electrical resistivity directly onto the first surface of the semiconductor stack structure.

Abstract translation: 公开了一种半导体器件及其制造方法。 半导体器件包括具有第一表面和第二表面的半导体堆叠结构。 具有高导热性和高电阻率的聚合物基板设置在半导体堆叠结构的第一表面上。 一种方法包括提供具有与晶片把手直接接触的第一表面的半导体堆叠结构。 下一步涉及去除晶片把手以暴露半导体堆叠结构的第一表面。 以下步骤包括将具有高导热性和高电阻率的聚合物基材物质直接设置在半导体堆叠结构的第一表面上。

公开(公告)号：US20140252566A1

公开(公告)日：2014-09-11

申请号：US14260909

申请日：2014-04-24

Applicant: RF Micro Devices, Inc.

Inventor： Daniel Charles Kerr ,  Julio Costa ,  Michael Carroll ,  Don Willis ,  Elizabeth Glass

IPC: H01L29/02 ,  H01L21/02

CPC classification number: H01L21/0237 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3192 ,  H01L23/36 ,  H01L23/3737 ,  H01L29/78606 ,  H01L2224/13022

Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure having a first surface and a second surface. A first polymer having a high thermal conductivity and a high electrical resistivity is disposed on the first surface of the semiconductor stack structure. An exemplary method includes providing the semiconductor stack structure with the second surface in direct contact with a wafer handle. A next step involves removing the wafer handle to expose the second surface of the semiconductor stack structure. A following step includes disposing a second polymer having high thermal conductivity and high electrical resistivity directly onto the second surface of the semiconductor stack structure. Additional methods apply silicon nitride layers on the first surface and second surface of the semiconductor stack structure before disposing the first polymer and second polymer to realize the semiconductor device.

Abstract translation: 公开了一种半导体器件及其制造方法。 半导体器件包括具有第一表面和第二表面的半导体堆叠结构。 具有高导热性和高电阻率的第一聚合物设置在半导体堆叠结构的第一表面上。 一种示例性方法包括提供具有与晶片把手直接接触的第二表面的半导体堆叠结构。 下一步涉及去除晶片把手以暴露半导体堆叠结构的第二表面。 以下步骤包括将具有高导热性和高电阻率的第二聚合物直接设置在半导体堆叠结构的第二表面上。 在配置第一聚合物和第二聚合物以实现半导体器件之前，附加方法将氮化硅层应用于半导体叠层结构的第一表面和第二表面。

公开(公告)号：US20150340322A1

公开(公告)日：2015-11-26

申请号：US14721531

申请日：2015-05-26

Applicant: RF Micro Devices, Inc.

Inventor： Philip W. Mason ,  Michael Carroll ,  Julio C. Costa

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5329 ,  H01L21/823475 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An RF switch structure having reduced off-state capacitance is disclosed. The RF switch structure includes an RF switch branch having at least three transistors coupled in series within a device layer. Inter-metal dielectric (IMD) layers are disposed over the device layer. At least one of the IMD layers has an effective dielectric constant that is lower than 3.9. In one exemplary embodiment, the IMD layers are made of silicon dioxide having micro-voids. In another exemplary embodiment, the IMD layers are made of silicon dioxide that includes carbon doping. In either exemplary embodiment, an effective dielectric constant ranges from about 3.9 to around 2.0. In another exemplary embodiment, the IMD layers are made of silicon dioxide having trapped air bubbles that provide an effective dielectric constant that ranges from about 2.0 to 1.1.

Abstract translation: 公开了具有减小的截止状态电容的RF开关结构。 RF开关结构包括具有在器件层内串联耦合的至少三个晶体管的RF开关分支。 金属间电介质（IMD）层设置在器件层上。 至少一个IMD层具有低于3.9的有效介电常数。 在一个示例性实施例中，IMD层由具有微孔的二氧化硅制成。 在另一示例性实施例中，IMD层由包含碳掺杂的二氧化硅制成。 在任一示例性实施例中，有效介电常数范围为约3.9至约2.0。 在另一个示例性实施方案中，IMD层由具有捕获的气泡的二氧化硅制成，其提供范围为约2.0至1.1的有效介电常数。

公开(公告)号：US20140242760A1

公开(公告)日：2014-08-28

申请号：US14276370

申请日：2014-05-13

Applicant: RF Micro Devices, Inc.

Inventor： Michael Carroll ,  Daniel Charles Kerr ,  Christian Rye Iversen ,  Philip W. Mason ,  Julio Costa ,  Edward T. Spears

IPC: H01L21/84

CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/7833

Abstract: The present disclosure relates to a radio frequency (RF) switch that includes multiple body-contacted field effect transistor (FET) elements coupled in series. The FET elements may be formed using a thin-film semiconductor device layer, which is part of a thin-film semiconductor die. Conduction paths between the FET elements through the thin-film semiconductor device layer and through a substrate of the thin-film semiconductor die may be substantially eliminated by using insulating materials. Elimination of the conduction paths allows an RF signal across the RF switch to be divided across the series coupled FET elements, such that each FET element is subjected to only a portion of the RF signal. Further, each FET element is body-contacted and may receive reverse body biasing when the RF switch is in an OFF state, thereby reducing an OFF state drain-to-source capacitance of each FET element.

Abstract translation: 本发明涉及射频（RF）开关，其包括串联耦合的多个体接触场效应晶体管（FET）元件。 可以使用作为薄膜半导体管芯的一部分的薄膜半导体器件层来形成FET元件。 通过薄膜半导体器件层和通过薄膜半导体晶片的衬底的FET元件之间的导通路径可以通过使用绝缘材料基本上消除。 消除导通路径允许跨越RF开关的RF信号在串联耦合的FET元件之间被划分，使得每个FET元件仅受到RF信号的一部分的影响。 此外，当RF开关处于OFF状态时，每个FET元件被体接触并且可以接收反向主体偏置，从而降低每个FET元件的截止状态漏极 - 源极电容。

公开(公告)号：US20160023892A1

公开(公告)日：2016-01-28

申请号：US14805774

申请日：2015-07-22

Applicant: RF Micro Devices, Inc.

Inventor： Julio C. Costa ,  Michael Carroll ,  Jonathan Hale Hammond

IPC: B81B7/00

CPC classification number: B81B7/0064 ,  H01H1/0036

Abstract: The present disclosure relates to radio frequency (RF) microelectromechanical system (MEMS) device packaging, and specifically to reducing harmonic distortion caused by such packaging. In one embodiment, a die is provided that employs a gold-doped silicon substrate, wherein at least one RF MEMS device is disposed on the gold-doped silicon substrate. By employing the gold-doped silicon substrate, the packaging can achieve an exceptionally high resistivity without any additional expensive components, wherein the high resistivity has an associated low carrier lifetime. Notably, the low carrier lifetime corresponds to reduced harmonic distortion generated by the gold-doped silicon substrate, even when operating at high power. Thus, the gold-doped silicon substrate provides a less expensive packaging in which to place RF MEMS devices, wherein the packaging is capable of operating at high power with reduced harmonic distortion.

Abstract translation: 本公开涉及射频（RF）微机电系统（MEMS）设备封装，并且具体涉及减少由这种封装引起的谐波失真。 在一个实施例中，提供了一种使用金掺杂硅衬底的管芯，其中至少一个RF MEMS器件设置在掺金硅衬底上。 通过采用金掺杂硅衬底，封装可以实现非常高的电阻率，而没有任何额外的昂贵的组件，其中高电阻率具有相关联的低载流子寿命。 值得注意的是，低载流子寿命对应于由金掺杂硅衬底产生的减少的谐波失真，即使在高功率下操作。 因此，金掺杂硅衬底提供了一种较便宜的封装，其中放置RF MEMS器件，其中封装能够以较低功率运行并减少谐波失真。

公开(公告)号：US20150371905A1

公开(公告)日：2015-12-24

申请号：US14746005

申请日：2015-06-22

Applicant: RF Micro Devices, Inc.

Inventor： Michael Carroll ,  Julio C. Costa ,  Philip W. Mason ,  Edward T. Spears ,  Bill Rhyne

IPC: H01L21/84 ,  H01L21/304 ,  H01L21/683 ,  H01L29/10 ,  H01L27/12 ,  H01L23/00 ,  H01L29/167 ,  H01L21/78 ,  H01L27/092

CPC classification number: H01L21/84 ,  H01L21/6835 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/167 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/08225 ,  H01L2224/11002 ,  H01L2224/32225 ,  H01L2224/73251 ,  H01L2224/73253 ,  H01L2224/80006 ,  H01L2224/80009 ,  H01L2224/80205 ,  H01L2224/80893 ,  H01L2224/80896 ,  H01L2224/83005 ,  H01L2224/83805 ,  H01L2224/8389 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/15738 ,  H01L2924/00014 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2221/6835 ,  H01L2224/11003 ,  H01L21/78

Abstract: A method for manufacturing a semiconductor die includes providing an SOI semiconductor wafer including a substrate, an insulating layer over the substrate, and a device layer over the insulating layer. A surface of the SOI semiconductor wafer opposite the substrate is mounted to a temporary carrier mount, and the substrate is removed, leaving an exposed surface of the insulating layer. A high-resistivity gold-doped silicon substrate is then provided on the exposed surface of the insulating layer. By providing the high-resistivity gold-doped silicon substrate, an exceptionally high-resistivity substrate can be achieved, thereby minimizing field-dependent electrical interaction between the substrate and one or more semiconductor devices thereon. Accordingly, harmonic distortion in the semiconductor devices caused by the substrate will be reduced, thereby increasing the performance of the device.

Abstract translation: 一种半导体晶片的制造方法，其特征在于，在绝缘层上设置包括基板，绝缘层，绝缘层的SOI半导体晶片。 与衬底相对的SOI半导体晶片的表面安装到临时载体安装件，并且去除衬底，留下绝缘层的暴露表面。 然后在绝缘层的暴露表面上提供高电阻率金掺杂硅衬底。 通过提供高电阻率金掺杂硅衬底，可以实现特别高电阻率的衬底，从而最小化衬底与其上的一个或多个半导体器件之间的场相关电相互作用。 因此，由衬底引起的半导体器件中的谐波失真将减小，从而提高器件的性能。