公开(公告)号：US10759660B2

公开(公告)日：2020-09-01

申请号：US14711352

申请日：2015-05-13

Applicant: RF Micro Devices, Inc.

Inventor： Jonathan Hammond ,  Jan Edward Vandemeer ,  Julio Costa

IPC: B81C1/00

Abstract: A method for processing product wafers using carrier substrates is disclosed. The method includes a step of bonding a first carrier wafer to a first product wafer using a first temporary adhesion layer between a first carrier wafer surface and a first product wafer first surface. Another step includes bonding a second carrier wafer to a second product wafer using a second temporary adhesion layer between a second carrier wafer surface and a second product wafer surface. Another step includes bonding the first product wafer to the second product wafer using a permanent bond between a first product wafer second surface and a second product wafer first surface. In exemplary embodiments, at least one processing step is performed on the first product wafer after the first temporary carrier wafer is bonded to the first product wafer before the second product wafer is permanently bonded to the first product wafer.

公开(公告)号：US20150353348A1

公开(公告)日：2015-12-10

申请号：US14718408

申请日：2015-05-21

Applicant: RF Micro Devices, Inc.

Inventor： Jan Edward Vandemeer ,  Jonathan Hale Hammond

IPC: B81B7/00

CPC classification number: B81B7/0006 ,  B81B2201/014 ,  B81B2207/092 ,  B81B2207/095 ,  B81B2207/096 ,  B81C1/00269 ,  B81C1/00301 ,  B81C2203/0109 ,  B81C2203/035 ,  H01L2224/48137

Abstract: A glass wafer assembly is disclosed. In one aspect, the glass wafer assembly comprises a first glass wafer and a second glass wafer that are bonded by a conductive sealing ring. The conductive sealing ring defines a substantially hermetically sealed cavity between the first glass wafer and the second glass wafer. In another aspect, the first glass wafer and the second glass wafer each comprise a plurality of conductive through glass vias (TGVs). At least one active device is disposed in the substantially hermetically sealed cavity and can be electrically coupled to a conductive TGV in the first glass wafer and a conductive TGV in the second glass wafer to enable flexible electrical routing through the glass wafer assembly without wire bonding and over molding. As a result, it is possible to reduce footprint and height while improving radio frequency (RF) performance of the glass wafer assembly.

Abstract translation: 公开了一种玻璃晶片组件。 在一个方面，玻璃晶片组件包括通过导电密封环结合的第一玻璃晶片和第二玻璃晶片。 导电密封环在第一玻璃晶片和第二玻璃晶片之间限定基本上气密的空腔。 在另一方面，第一玻璃晶片和第二玻璃晶片各自包括多个导电透玻璃通孔（TGV）。 至少一个有源器件设置在基本上气密密封的空腔中，并且可以电耦合到第一玻璃晶片中的导电TGV和第二玻璃晶片中的导电TGV，以使得能够通过玻璃晶片组件的柔性电路径而不引线接合， 超模塑。 结果，可以在改善玻璃晶片组件的射频（RF）性能的同时减小占地面积和高度。

公开(公告)号：US20150329355A1

公开(公告)日：2015-11-19

申请号：US14711352

申请日：2015-05-13

Applicant: RF Micro Devices, Inc.

Inventor： Jonathan Hammond ,  Jan Edward Vandemeer ,  Julio Costa

IPC: B81C1/00

CPC classification number: B81C1/00269 ,  B81C1/0015 ,  B81C2201/0194 ,  B81C2203/0118 ,  B81C2203/0127

Abstract: A method for processing product wafers using carrier substrates is disclosed. The method includes a step of bonding a first carrier wafer to a first product wafer using a first temporary adhesion layer between a first carrier wafer surface and a first product wafer first surface. Another step includes bonding a second carrier wafer to a second product wafer using a second temporary adhesion layer between a second carrier wafer surface and a second product wafer surface. Another step includes bonding the first product wafer to the second product wafer using a permanent bond between a first product wafer second surface and a second product wafer first surface. In exemplary embodiments, at least one processing step is performed on the first product wafer after the first temporary carrier wafer is bonded to the first product wafer before the second product wafer is permanently bonded to the first product wafer.

Abstract translation: 公开了一种使用载体衬底处理产品晶片的方法。 该方法包括使用第一载体晶片表面和第一产品晶片第一表面之间的第一临时粘合层将第一载体晶片接合到第一产品晶片的步骤。 另一步骤包括使用第二载体晶片表面和第二产品晶片表面之间的第二临时粘合层将第二载体晶片接合到第二产品晶片。 另一步骤包括使用第一产品晶片第二表面和第二产品晶片第一表面之间的永久接合将第一产品晶片连接到第二产品晶片。 在示例性实施例中，在第二产品晶片永久地结合到第一产品晶片之前，在第一临时载体晶片被结合到第一产品晶片之后，在第一产品晶片上执行至​​少一个处理步骤。

公开(公告)号：US20160343604A1

公开(公告)日：2016-11-24

申请号：US15085185

申请日：2016-03-30

Applicant: RF Micro Devices, Inc.

Inventor： Julio C. Costa ,  Jan Edward Vandemeer

IPC: H01L21/687 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/0692 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76256 ,  H01L29/0649 ,  H01L29/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368

Abstract: The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure includes a silicon handle layer, a first silicon oxide layer over the silicon handle layer, a buried dielectric layer over the first silicon oxide layer, where the buried dielectric layer is not formed from silicon oxide, a second silicon oxide layer over the buried dielectric layer, and a silicon epitaxy layer over the second silicon oxide layer. The buried dielectric layer provides extremely selective etch stop characteristics with respect to etching chemistries for silicon and silicon oxide.

Abstract translation: 本公开内容涉及一种具有用于后处理硅手柄消除的掩埋介质层的衬底结构。 所述衬底结构包括硅手柄层，所述硅手柄层上的第一氧化硅层，所述第一氧化硅层上的掩埋介电层，其中所述掩埋介电层不由氧化硅形成，所述第二氧化硅层 掩埋介电层和在第二氧化硅层上的硅外延层。 相对于硅和氧化硅的蚀刻化学性质，埋入的介电层提供非常选择性的蚀刻停止特性。

公开(公告)号：US09806192B2

公开(公告)日：2017-10-31

申请号：US15133669

申请日：2016-04-20

Applicant: RF Micro Devices, Inc.

Inventor： Philip W. Mason ,  Michael Carroll ,  Julio C. Costa ,  Jan Edward Vandemeer ,  Daniel Charles Kerr

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L23/66

CPC classification number: H01L29/7838 ,  H01L23/66 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78654

Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate structure with a buried dielectric layer for radio frequency (RF) complementary metal-oxide semiconductor (CMOS) switch fabrications. The buried dielectric layer suppresses back-gate transistors in the RF CMOS switches fabricated on the SOI substrate structure. The SOI substrate structure includes a silicon handle layer, a silicon oxide layer over the silicon handle layer, a buried dielectric layer over the silicon oxide layer, and a silicon epitaxy layer directly over the buried dielectric layer.

公开(公告)号：US20160380101A1

公开(公告)日：2016-12-29

申请号：US15133669

申请日：2016-04-20

Applicant: RF Micro Devices, Inc.

Inventor： Philip W. Mason ,  Michael Carroll ,  Julio C. Costa ,  Jan Edward Vandemeer ,  Daniel Charles Kerr

IPC: H01L29/78 ,  H01L27/12 ,  H01L23/66 ,  H01L27/092

CPC classification number: H01L29/7838 ,  H01L23/66 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78654

Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate structure with a buried dielectric layer for radio frequency (RF) complementary metal-oxide semiconductor (CMOS) switch fabrications. The buried dielectric layer suppresses back-gate transistors in the RF CMOS switches fabricated on the SOI substrate structure. The SOI substrate structure includes a silicon handle layer, a silicon oxide layer over the silicon handle layer, a buried dielectric layer over the silicon oxide layer, and a silicon epitaxy layer directly over the buried dielectric layer.

Abstract translation: 本公开涉及具有用于射频（RF）互补金属氧化物半导体（CMOS）开关制造的掩埋介电层的绝缘体上硅（SOI）衬底结构。 掩埋介质层抑制在SOI衬底结构上制造的RF CMOS开关中的背栅晶体管。 SOI衬底结构包括硅手柄层，硅手柄层上的氧化硅层，氧化硅层上的掩埋电介质层，以及直接在掩埋电介质层上的硅外延层。

公开(公告)号：US09688529B2

公开(公告)日：2017-06-27

申请号：US14718408

申请日：2015-05-21

Applicant: RF Micro Devices, Inc.

Inventor： Jan Edward Vandemeer ,  Jonathan Hale Hammond

IPC: B81B3/00 ,  B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0006 ,  B81B2201/014 ,  B81B2207/092 ,  B81B2207/095 ,  B81B2207/096 ,  B81C1/00269 ,  B81C1/00301 ,  B81C2203/0109 ,  B81C2203/035 ,  H01L2224/48137

Abstract: A glass wafer assembly is disclosed. In one aspect, the glass wafer assembly comprises a first glass wafer and a second glass wafer that are bonded by a conductive sealing ring. The conductive sealing ring defines a substantially hermetically sealed cavity between the first glass wafer and the second glass wafer. In another aspect, the first glass wafer and the second glass wafer each comprise a plurality of conductive through glass vias (TGVs). At least one active device is disposed in the substantially hermetically sealed cavity and can be electrically coupled to a conductive TGV in the first glass wafer and a conductive TGV in the second glass wafer to enable flexible electrical routing through the glass wafer assembly without wire bonding and over molding. As a result, it is possible to reduce footprint and height while improving radio frequency (RF) performance of the glass wafer assembly.

公开(公告)号：US20160219704A1

公开(公告)日：2016-07-28

申请号：US15008691

申请日：2016-01-28

Applicant: RF Micro Devices, Inc.

Inventor： Jan Edward Vandemeer ,  Khoi Tam Vu

IPC: H05K1/11 ,  H01L21/768 ,  H05K3/46 ,  H05K1/03 ,  H05K1/02 ,  H01L23/538 ,  H01L21/56

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/426 ,  H05K2201/10378 ,  H01L2924/00

Abstract: Hermetically sealed through vias (TVs) are disclosed. In one aspect, an hourglass TV is first created in a substrate. The hourglass TV has a waist opening. A conductive conformal coating covers at least a portion of an interior wall of the hourglass TV. The conductive conformal coating also completely fills the waist opening to provide a hermetic seal between an upper opening and a lower opening of the hourglass TV, thus creating the hermetically sealed TV. The combination of the hourglass shape, which provides a narrowing waist, and using the conformal coating process, facilitates the natural accumulation of the conductive conformal coating material in and about the waist opening. Creating hermetically sealed TVs in this manner leads to lower costs, shortened process and plating times, and increased production throughput compared to conventional processes for creating the hermetically sealed TVs in substrates.

Abstract translation: 透过通孔（电视机）密封。 在一个方面，首先在基板中产生沙漏电视。 沙漏电视有一个腰部开口。 导电保形涂层覆盖沙漏电视的内壁的至少一部分。 导电保形涂层还完全填充腰部开口，以在沙漏电视的上部开口和下部开口之间提供密封，从而形成密封的电视机。 提供窄腰的沙漏形状和使用保形涂布工艺的组合有助于导电保形涂层材料在腰部开口内和周围的自然积聚。 与在基板中形成密封电视的常规工艺相比，以这种方式创建密封电视导致成本降低，工艺和电镀时间缩短，生产量增加。