公开(公告)号：US20140111919A1

公开(公告)日：2014-04-24

申请号：US14049283

申请日：2013-10-09

申请人： Seiko Epson Corporation

发明人： Hideo Miyasaka ,  Kazuhisa Hashimoto

IPC分类号： H05K13/04 ,  H05K5/03

CPC分类号： H05K13/046 ,  H01L21/50 ,  H01L23/10 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L41/23 ,  H01L2224/08225 ,  H01L2224/32227 ,  H01L2224/80205 ,  H01L2224/83205 ,  H01L2924/12034 ,  H01L2924/12042 ,  H01L2924/16195 ,  H03H9/1021 ,  H05K5/03 ,  H01L2924/00014 ,  H01L2924/00

摘要： A bonding method of a container having a base substrate, and a lid member adapted to form a space with the base substrate includes: providing the base substrate and the lid member, arranging the lid member so as to overlap a bonding area of the base substrate, making a pressing member have contact with an exterior surface of an area of the lid member surrounded by the bonding area, and performing bonding by irradiating the lid member with an energy beam in the state of making the pressing member have contact with the lid member.

摘要翻译： 具有基底的容器的接合方法和适于与基底基板形成空间的盖构件包括：设置基底基板和盖构件，将盖构件设置成与基底基板的接合面重叠 使得按压部件与由所述接合区域包围的所述盖部件的区域的外表面接触，并且在使所述按压部件与所述盖部件接触的状态下通过用能量束照射所述盖部件来进行接合 。

公开(公告)号：US20080150108A1

公开(公告)日：2008-06-26

申请号：US11964460

申请日：2007-12-26

申请人： Miho Mochizuki

发明人： Miho Mochizuki

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/3107 ,  H01L23/481 ,  H01L23/4951 ,  H01L23/49548 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/08245 ,  H01L2224/80205 ,  H01L2224/80805 ,  H01L2224/8083 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/131 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor package includes: a semiconductor chip and a plurality of frames. A plurality of electrodes are formed on a surface of the semiconductor chip. The plurality of frames are connected to the plurality of electrodes. The plurality of frames are formed by dividing one conductive plate by etching.

摘要翻译： 半导体封装包括：半导体芯片和多个框架。 多个电极形成在半导体芯片的表面上。 多个框架连接到多个电极。 多个框架通过蚀刻分割一个导电板而形成。

公开(公告)号：US20240162126A1

公开(公告)日：2024-05-16

申请号：US18054919

申请日：2022-11-14

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Wu-Der YANG

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/08225 ,  H01L2224/32225 ,  H01L2224/80205 ,  H01L2224/838

摘要： The present disclosure is related to a semiconductor package. The semiconductor package includes a substrate and a semiconductor chip. The substrate includes a window through a center portion of the substrate, in which the substrate has an inner sidewall surrounding the window and a conductive foil located on a top surface of the substrate, in which the conductive foil extends beyond the inner sidewall of the substrate. The semiconductor chip is located on the top surface of the substrate, in which the conductive foil is located between the substrate and the semiconductor chip, and the semiconductor chip has a bonding pad electrically connected to the conductive foil.

公开(公告)号：US20150044496A1

公开(公告)日：2015-02-12

申请号：US14370931

申请日：2013-03-01

申请人： KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO

发明人： Tadashi Oshima ,  Hisaaki Takao ,  Hirofumi Ito

IPC分类号： B23K20/10 ,  B32B7/04 ,  B32B15/01

CPC分类号： B23K20/10 ,  B32B7/04 ,  B32B15/01 ,  B32B2250/02 ,  B32B2311/24 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/80205 ,  H01L2224/80365 ,  H01L2224/80385 ,  H01L2224/81205 ,  H01L2224/81365 ,  H01L2224/81385 ,  H01L2224/83205 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2924/12042 ,  Y10T428/12472 ,  H01L2924/00012 ,  H01L2924/00

摘要： A jointed body that has been solid-phase jointed at normal temperature and that has a non-conventional structure is presented. The jointed body is formed by solid-phase joining a first jointed member to a second jointed member, and has a junction interface between the first member and the second member. This jointed body includes an average crystal grain size in a near interface structure that constitutes a near interface area having a total width of 20 micrometers and extending at both sides of the junction interface as a center is 75-100% of an average crystal grain size in an around interface structure that constitutes around interface areas located at both outer sides of the near interface area. In the jointed body, the near interface structure after the joining is almost the same as the structure before the joining, allowing the jointed body to exert similar characteristics to the jointed members.

摘要翻译： 提出了在常温下固相接合并具有非常规结构的接合体。 接合体通过将第一接合构件固相接合到第二接合构件而形成，并且在第一构件和第二构件之间具有接合界面。 该接合体包括近界面结构中的平均晶粒尺寸，其构成总宽度为20微米的近界面区域，并且在作为中心的接合界面的两侧延伸为平均晶粒尺寸的75-100％ 在围绕接口结构的周边界面结构中，该界面结构围绕位于近界面区域的两个外侧的界面区域。 在接合体中，接合后的接近结构几乎与接合前的结构相同，使得接合体对接合部件施加相似的特性。

公开(公告)号：US20230225055A1

公开(公告)日：2023-07-13

申请号：US18184837

申请日：2023-03-16

申请人： IMBERATEK, LLC

发明人： Risto TUOMINEN ,  Petteri PALM

IPC分类号： H05K1/18 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC分类号： H05K1/185 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/5385 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L2224/05624 ,  H01L2224/08225 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/80203 ,  H01L2224/80205 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2924/15153 ,  H05K2201/042 ,  H05K2201/0367

摘要： The present invention relates to an electronic module. In particular, to an electronic module which includes one or more components embedded in an installation base. The electronic module can be a module like a circuit board, which includes several components, which are connected to each other electrically, through conducting structures manufactured in the module. The components can be passive components, microcircuits, semiconductor components, or other similar components. Components that are typically connected to a circuit board form one group of components. Another important group of components are components that are typically packaged for connection to a circuit board. The electronic modules to which the invention relates can, of course, also include other types of components.

公开(公告)号：US09821406B2

公开(公告)日：2017-11-21

申请号：US14370931

申请日：2013-03-01

申请人： KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO

发明人： Tadashi Oshima ,  Hisaaki Takao ,  Hirofumi Ito

IPC分类号： B23K20/10 ,  B32B15/01 ,  B23K20/12 ,  H01L23/00 ,  B32B7/04

CPC分类号： B23K20/10 ,  B32B7/04 ,  B32B15/01 ,  B32B2250/02 ,  B32B2311/24 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/80205 ,  H01L2224/80365 ,  H01L2224/80385 ,  H01L2224/81205 ,  H01L2224/81365 ,  H01L2224/81385 ,  H01L2224/83205 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2924/12042 ,  Y10T428/12472 ,  H01L2924/00012 ,  H01L2924/00

摘要： A jointed body that has been solid-phase jointed at normal temperature and that has a non-conventional structure is presented. The jointed body is formed by solid-phase joining a first jointed member to a second jointed member, and has a junction interface between the first member and the second member. This jointed body includes an average crystal grain size in a near interface structure that constitutes a near interface area having a total width of 20 micrometers and extending at both sides of the junction interface as a center is 75-100% of an average crystal grain size in an around interface structure that constitutes around interface areas located at both outer sides of the near interface area. In the jointed body, the near interface structure after the joining is almost the same as the structure before the joining, allowing the jointed body to exert similar characteristics to the jointed members.

公开(公告)号：US20150371905A1

公开(公告)日：2015-12-24

申请号：US14746005

申请日：2015-06-22

申请人： RF Micro Devices, Inc.

发明人： Michael Carroll ,  Julio C. Costa ,  Philip W. Mason ,  Edward T. Spears ,  Bill Rhyne

IPC分类号： H01L21/84 ,  H01L21/304 ,  H01L21/683 ,  H01L29/10 ,  H01L27/12 ,  H01L23/00 ,  H01L29/167 ,  H01L21/78 ,  H01L27/092

CPC分类号： H01L21/84 ,  H01L21/6835 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/167 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/08225 ,  H01L2224/11002 ,  H01L2224/32225 ,  H01L2224/73251 ,  H01L2224/73253 ,  H01L2224/80006 ,  H01L2224/80009 ,  H01L2224/80205 ,  H01L2224/80893 ,  H01L2224/80896 ,  H01L2224/83005 ,  H01L2224/83805 ,  H01L2224/8389 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/15738 ,  H01L2924/00014 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2221/6835 ,  H01L2224/11003 ,  H01L21/78

摘要： A method for manufacturing a semiconductor die includes providing an SOI semiconductor wafer including a substrate, an insulating layer over the substrate, and a device layer over the insulating layer. A surface of the SOI semiconductor wafer opposite the substrate is mounted to a temporary carrier mount, and the substrate is removed, leaving an exposed surface of the insulating layer. A high-resistivity gold-doped silicon substrate is then provided on the exposed surface of the insulating layer. By providing the high-resistivity gold-doped silicon substrate, an exceptionally high-resistivity substrate can be achieved, thereby minimizing field-dependent electrical interaction between the substrate and one or more semiconductor devices thereon. Accordingly, harmonic distortion in the semiconductor devices caused by the substrate will be reduced, thereby increasing the performance of the device.

摘要翻译： 一种半导体晶片的制造方法，其特征在于，在绝缘层上设置包括基板，绝缘层，绝缘层的SOI半导体晶片。 与衬底相对的SOI半导体晶片的表面安装到临时载体安装件，并且去除衬底，留下绝缘层的暴露表面。 然后在绝缘层的暴露表面上提供高电阻率金掺杂硅衬底。 通过提供高电阻率金掺杂硅衬底，可以实现特别高电阻率的衬底，从而最小化衬底与其上的一个或多个半导体器件之间的场相关电相互作用。 因此，由衬底引起的半导体器件中的谐波失真将减小，从而提高器件的性能。

公开(公告)号：US20240222316A1

公开(公告)日：2024-07-04

申请号：US18400697

申请日：2023-12-29

申请人： Adeia Semiconductor Bonding Technologies Inc.

发明人： Pawel Mrozek ,  Gaius Gillman Fountain, JR.

IPC分类号： H01L23/00

CPC分类号： H01L24/80 ,  H01L2224/80205 ,  H01L2224/80895 ,  H01L2224/80896

摘要： A method of forming direct metal bonds between a first device and a second device is provided. The method may include heating a workpiece to a temperature between 40 C and 150 C, and directing sonic energy towards the heated workpiece. Here, the workpiece may include the first device and the second device directly bonded to the first device through a dielectric material interface.

公开(公告)号：US08969200B2

公开(公告)日：2015-03-03

申请号：US13445636

申请日：2012-04-12

申请人： Jeremiah Hebding ,  Megha Rao ,  Colin McDonough ,  Matthew Smalley ,  Douglas Duane Coolbaugh ,  Joseph Piccirillo, Jr. ,  Stephen G. Bennett ,  Michael Liehr ,  Daniel Pascual

发明人： Jeremiah Hebding ,  Megha Rao ,  Colin McDonough ,  Matthew Smalley ,  Douglas Duane Coolbaugh ,  Joseph Piccirillo, Jr. ,  Stephen G. Bennett ,  Michael Liehr ,  Daniel Pascual

IPC分类号： H01L21/44

CPC分类号： H01L25/0652 ,  H01L21/76229 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/131 ,  H01L2224/80097 ,  H01L2224/80203 ,  H01L2224/80205 ,  H01L2224/80895 ,  H01L2224/9205 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/80 ,  H01L2924/00

摘要： An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer.

摘要翻译： 提供了一种在设备接触处理之前将TSV集成到设备中的装置和方法。 该装置包括半导体层; 安装在半导体层的顶表面上的一个或多个CMOS器件; 集成到器件晶片的半导体层中的一个或多个TSV; 在TSV上施加至少一个金属层; 以及安装在所述至少一个金属层的顶层上的一个或多个接合焊盘，其中所述至少一个金属层被布置成能够将所述一个或多个接合焊盘放置在用于结合到第二器件晶片的指定位置。 该方法包括获得半导体材料晶片，在晶片上进行线前处理; 在晶片中提供一个或多个TSV; 在晶片上进行中间线处理; 并在晶片上执行线路处理的后端。

公开(公告)号：US08927335B2

公开(公告)日：2015-01-06

申请号：US13496024

申请日：2010-09-03

申请人： Markus Wimplinger

发明人： Markus Wimplinger

IPC分类号： H01L21/78 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/74 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/74 ,  H01L2224/7598 ,  H01L2224/80006 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80205 ,  H01L2224/80805 ,  H01L2224/80815 ,  H01L2224/8082 ,  H01L2224/80907 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81065 ,  H01L2224/81075 ,  H01L2224/81205 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2224/81907 ,  H01L2224/83005 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/83205 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/8382 ,  H01L2224/83907 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05552

摘要： Method for bonding of a plurality of chips onto a base wafer which contains chips on the front, the chips being stacked in at least one layer on the back of the base wafer and electrically conductive connections are established between the vertically adjacent chips, with the following steps: a) fixing of the front of the base wafer on a carrier, b) placing at least one layer of chips in defined positions on the back of the base wafer, and c) heat treatment of the chips on the base wafer fixed on the carrier, characterized in that prior to step c) at least partial separation of the chips of the base wafer into separated chip stack sections of the base after takes place.

摘要翻译： 将多个芯片接合到包含前面的芯片的基底晶片上的方法，将芯片堆叠在基底晶片的背面上的至少一层中，并且在垂直相邻的芯片之间建立导电连接，具有以下 步骤：a）将基底晶片的前部固定在载体上，b）将至少一层芯片放置在基底晶片的背面上的限定位置，以及c）将固定在基底晶片上的基片上的芯片进行热处理 载体，其特征在于，在步骤c）之前，在发生基底晶片的芯片至少部分分离成基底的分离的芯片堆叠部分之后。