公开(公告)号：US20240014159A1

公开(公告)日：2024-01-11

申请号：US18471358

申请日：2023-09-21

Applicant: ROHM CO., LTD.

Inventor： Bungo TANAKA ,  Keiji WADA ,  Satoshi KAGEYAMA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/495 ,  H01L23/528

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L24/05 ,  H01L23/5226 ,  H01L23/49548 ,  H01L23/5283 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/03 ,  H01L2924/01046 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/1318 ,  H01L2224/13176 ,  H01L2224/13171 ,  H01L2224/05582 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01029 ,  H01L2924/01022 ,  H01L2924/04941 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01042 ,  H01L2924/01024 ,  H01L2924/01044 ,  H01L2924/01028 ,  H01L24/83 ,  H01L24/32 ,  H01L2224/83801 ,  H01L2224/05147 ,  H01L2224/48465 ,  H01L24/73 ,  H01L24/29 ,  H01L23/562 ,  H01L2224/29101 ,  H01L2224/05012 ,  H01L2224/45124 ,  H01L2224/73265 ,  H01L2224/45144 ,  H01L2924/181 ,  H01L23/53223

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

公开(公告)号：US20230091632A1

公开(公告)日：2023-03-23

申请号：US17816826

申请日：2022-08-02

Applicant: ROHM CO., LTD.

Inventor： Satoshi KAGEYAMA ,  Hiroyuki SHINKAI ,  Yoshihisa TAKADA ,  Natsuki SAKAMOTO

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor device includes: a resin layer having a resin main surface; a mounting wiring layer arranged on the resin main surface, and having a mounting wiring main surface facing the same side as the resin main surface and a mounting wiring back surface facing the side of the resin main surface; a semiconductor element including an element wiring layer which is mounted on the mounting wiring main surface, has an element wiring main surface facing the side of the resin layer, and is connected to the mounting wiring layer; and a sealing resin which seals the mounting wiring layer and the semiconductor element, wherein the mounting wiring main surface and the element wiring main surface are rough surfaces having a larger surface roughness than the mounting wiring back surface.

公开(公告)号：US20210035889A1

公开(公告)日：2021-02-04

申请号：US16939502

申请日：2020-07-27

Applicant: ROHM CO., LTD.

Inventor： Satoshi KAGEYAMA ,  Yoshihisa TAKADA

IPC: H01L23/488 ,  H01L23/00 ,  H01L23/04 ,  H01L23/12

Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.

公开(公告)号：US20130300001A1

公开(公告)日：2013-11-14

申请号：US13937459

申请日：2013-07-09

Applicant: ROHM CO., LTD.

Inventor： Satoshi KAGEYAMA ,  Yuichi NAKAO

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 μm, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.

公开(公告)号：US20250079369A1

公开(公告)日：2025-03-06

申请号：US18951967

申请日：2024-11-19

Applicant: ROHM CO., LTD.

Inventor： Bungo TANAKA ,  Keiji WADA ,  Satoshi KAGEYAMA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

公开(公告)号：US20230102799A1

公开(公告)日：2023-03-30

申请号：US18073295

申请日：2022-12-01

Applicant: ROHM CO., LTD.

Inventor： Bungo TANAKA ,  Keiji WADA ,  Satoshi KAGEYAMA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/495 ,  H01L23/528

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

公开(公告)号：US20200235064A1

公开(公告)日：2020-07-23

申请号：US16842548

申请日：2020-04-07

Applicant: ROHM CO., LTD.

Inventor： Bungo TANAKA ,  Keiji WADA ,  Satoshi KAGEYAMA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/495 ,  H01L23/528

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

公开(公告)号：US20190393177A1

公开(公告)日：2019-12-26

申请号：US16561747

申请日：2019-09-05

Applicant: ROHM CO., LTD.

Inventor： Bungo TANAKA ,  Keiji WADA ,  Satoshi KAGEYAMA

IPC: H01L23/00 ,  H01L23/31

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

公开(公告)号：US20160225711A1

公开(公告)日：2016-08-04

申请号：US15098351

申请日：2016-04-14

Applicant: ROHM CO., LTD.

Inventor： Yuichi NAKAO ,  Satoshi KAGEYAMA ,  Masaru NAITOU

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/528 ,  B23D51/125 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/05 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.

Abstract translation: 半导体器件包括半导体衬底，层叠在半导体衬底上的第一绝缘层，嵌入第一绝缘层的引线形成区域中的第一金属布线图案，层压在第一绝缘层上的第二绝缘层，第二绝缘层 埋设在第二绝缘层的导线形成区域中的布线图案和嵌入在与第二绝缘层的引线形成区域相对的布线对置区域中的第一伪金属图案以及与第二绝缘层相对的非线对向区域 除了第二绝缘层的导线形成区域之外的非线形成区域，线对向区域和非线对置区域分别位于除线形成区域之外的非线形成区域中 第一绝缘层。

公开(公告)号：US20150287678A1

公开(公告)日：2015-10-08

申请号：US14742817

申请日：2015-06-18

Applicant: ROHM CO., LTD.

Inventor： Satoshi KAGEYAMA ,  Yuichi NAKAO

IPC: H01L23/525 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5223 ,  H01L23/5258 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.

Abstract translation: 半导体器件包括由导电材料制成的下布线层; 上层布线层，形成在上层中，比下布线层形成; 以及熔丝膜，所述熔丝膜的至少一部分形成在其中形成用于连接所述下布线层和所述上布线层的插塞的插塞形成层中，并且由包含除了所述下布线层和所述上布线层之外的金属材料的导电材料制成 铜。