公开(公告)号：US20150067259A1

公开(公告)日：2015-03-05

申请号：US14013220

申请日：2013-08-29

申请人： Ren Wang ,  Kevin B. Theobald ,  Zeshan A. Chishti ,  Zhaojuan Bian ,  Aamer Jaleel ,  Tsung-Yuan C. Tai

发明人： Ren Wang ,  Kevin B. Theobald ,  Zeshan A. Chishti ,  Zhaojuan Bian ,  Aamer Jaleel ,  Tsung-Yuan C. Tai

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0895 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

摘要： Systems and methods for managing shared cache by multi-core processor. An example processing system comprises: a plurality of processing cores, each processing core communicatively coupled to a last level cache (LLC) slice; and a cache control logic coupled to the plurality of processing cores, the cache control logic configured to perform one of: making an LLC slice of an inactive processing core available to an active processing core or power gating the LLC slice, based on estimating cache requirements by active processing cores.

摘要翻译： 通过多核处理器管理共享缓存的系统和方法。 一个示例处理系统包括：多个处理核心，每个处理核心通信地耦合到最后一级高速缓存（LLC）片; 以及耦合到所述多个处理核心的高速缓存控制逻辑，所述高速缓存控制逻辑被配置为执行下列之一：基于估计高速缓存需求，使非活动处理核心的LLC片可用于活动处理核心或门控所述LLC片段 通过主动处理核心。

公开(公告)号：US20210004328A1

公开(公告)日：2021-01-07

申请号：US17027248

申请日：2020-09-21

申请人： Ren Wang ,  Andrew J. Herdrich ,  Yen-cheng Liu ,  Herbert H. Hum ,  Jong Soo Park ,  Christopher J. Hughes ,  Namakkal N. Venkatesan ,  Adrian C. Moga ,  Aamer Jaleel ,  Zeshan A. Chishti ,  Mesut A. Ergin ,  Jr-shian Tsai ,  Alexander W. Min ,  Tsung-yuan C. Tai ,  Christian Maciocco ,  Rajesh Sankaran

发明人： Ren Wang ,  Andrew J. Herdrich ,  Yen-cheng Liu ,  Herbert H. Hum ,  Jong Soo Park ,  Christopher J. Hughes ,  Namakkal N. Venkatesan ,  Adrian C. Moga ,  Aamer Jaleel ,  Zeshan A. Chishti ,  Mesut A. Ergin ,  Jr-shian Tsai ,  Alexander W. Min ,  Tsung-yuan C. Tai ,  Christian Maciocco ,  Rajesh Sankaran

IPC分类号： G06F12/0842 ,  G06F12/0831 ,  G06F12/0893 ,  G06F12/109 ,  G06F12/0813 ,  G06F9/455

摘要： Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

公开(公告)号：US20150234663A1

公开(公告)日：2015-08-20

申请号：US14181032

申请日：2014-02-14

申请人： Zeshan A. Chishti ,  Christopher B. Wilkerson ,  Seth Pugsley ,  Peng-Fei Chuang ,  Robert L. Scott ,  Aamer Jaleel ,  Shih-Lien L. Lu ,  Kingsum Chow

发明人： Zeshan A. Chishti ,  Christopher B. Wilkerson ,  Seth Pugsley ,  Peng-Fei Chuang ,  Robert L. Scott ,  Aamer Jaleel ,  Shih-Lien L. Lu ,  Kingsum Chow

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/383 ,  G06F2212/6026

摘要： A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

摘要翻译： 处理器包括高速缓存，根据预取器算法选择信息的预取器模块以及预取器算法选择模块。 预取器算法选择模块包括选择候选预取器算法的逻辑，当由预取器模块执行时，确定并存储候选预取器算法的预测存储器访问的存储器地址，确定在存储器操作期间访问的高速缓存行，并且评估所确定的高速缓存行是否匹配 存储的存储器地址。 预取器算法选择模块还包括用于调整候选预取器算法的准确率的逻辑，将精度比与阈值精度比进行比较，并且确定是否将第一候选预取器算法应用于预取器模块。

公开(公告)号：US09378021B2

公开(公告)日：2016-06-28

申请号：US14181032

申请日：2014-02-14

申请人： Zeshan A. Chishti ,  Christopher B. Wilkerson ,  Seth Pugsley ,  Peng-Fei Chuang ,  Robert L. Scott ,  Aamer Jaleel ,  Shih-Lien L. Lu ,  Kingsum Chow

发明人： Zeshan A. Chishti ,  Christopher B. Wilkerson ,  Seth Pugsley ,  Peng-Fei Chuang ,  Robert L. Scott ,  Aamer Jaleel ,  Shih-Lien L. Lu ,  Kingsum Chow

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/00

CPC分类号： G06F12/0862 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/383 ,  G06F2212/6026

摘要： A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

摘要翻译： 处理器包括高速缓存，根据预取器算法选择信息的预取器模块以及预取器算法选择模块。 预取器算法选择模块包括选择候选预取器算法的逻辑，当由预取器模块执行时，确定并存储候选预取器算法的预测存储器访问的存储器地址，确定在存储器操作期间访问的高速缓存行，并且评估所确定的高速缓存行是否匹配 存储的存储器地址。 预取器算法选择模块还包括用于调整候选预取器算法的准确率的逻辑，将精度比与阈值精度比进行比较，并且确定是否将第一候选预取器算法应用于预取器模块。

公开(公告)号：US20140173206A1

公开(公告)日：2014-06-19

申请号：US13785228

申请日：2013-03-05

申请人： Ren Wang ,  Ahmad Samih ,  Eric Delano ,  Pinkesh J. Shah ,  Zeshan A. Chishti ,  Christian Maciocco ,  Tsung-Yuan Charlie Tai

发明人： Ren Wang ,  Ahmad Samih ,  Eric Delano ,  Pinkesh J. Shah ,  Zeshan A. Chishti ,  Christian Maciocco ,  Tsung-Yuan Charlie Tai

IPC分类号： G06F12/08

CPC分类号： G06F12/0802 ,  G06F1/32 ,  G06F1/3215 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0811 ,  G06F2212/1028 ,  Y02D10/13

摘要： In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

公开(公告)号：US20140173207A1

公开(公告)日：2014-06-19

申请号：US13715613

申请日：2012-12-14

申请人： Ren Wang ,  Ahmad Samih ,  Eric Delano ,  Pinkesh J. Shah ,  Zeshan A. Chishti ,  Christian Maciocco ,  Tsung-Yuan Charlie Tai

发明人： Ren Wang ,  Ahmad Samih ,  Eric Delano ,  Pinkesh J. Shah ,  Zeshan A. Chishti ,  Christian Maciocco ,  Tsung-Yuan Charlie Tai

IPC分类号： G06F12/08

CPC分类号： G06F12/0802 ,  G06F1/32 ,  G06F1/3215 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0811 ,  G06F2212/1028 ,  Y02D10/13

摘要： In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括多个瓦片，每个瓦片包括核心和瓦片高速缓存层级。 该瓦片高速缓存层级包括第一级高速缓存，中级缓存（MLC）和最后级高速缓存（LLC），并且这些高速缓存中的每一个对于该瓦片是私有的。 耦合到瓦片的控制器包括高速缓存功率控制逻辑，用于至少部分地基于该信息来接收关于瓦片的核心和瓦片高速缓存层级的利用信息，并且使瓦片的LLC独立地进行电源门控。 描述和要求保护其他实施例。

公开(公告)号：US08276142B2

公开(公告)日：2012-09-25

申请号：US12587597

申请日：2009-10-09

申请人： Alaa R. Alameldeen ,  Zeshan A. Chishti

发明人： Alaa R. Alameldeen ,  Zeshan A. Chishti

IPC分类号： G06F9/46

CPC分类号： G06F9/505 ,  G06F2209/501

摘要： A method, device, and system are disclosed. In one embodiment the method includes scheduling a thread to run on first core of a multi-core processor. The determination as to which core the thread is scheduled on uses one or more processes. These processes may include ranking all of the cores specific to a workload of the thread, establishing a current utilization of each core of the multi-core processor, and calculating an inter-core migration cost for the thread.

摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括调度在多核处理器的第一核上运行的线程。 对线程安排的核心的确定使用一个或多个进程。 这些过程可以包括对线程工作负载特有的所有核心进行排序，建立多核处理器的每个核心的当前利用率，以及计算线程的核心间迁移成本。

公开(公告)号：US20150149714A1

公开(公告)日：2015-05-28

申请号：US14090056

申请日：2013-11-26

申请人： Seth H. Pugsley ,  Robert L. Scott ,  Zeshan A. Chishti ,  Peng-Fei Chuang ,  Khun Ban ,  Christopher B. Wilkerson ,  Shih-Lien L. Lu ,  Kingsum Chow

发明人： Seth H. Pugsley ,  Robert L. Scott ,  Zeshan A. Chishti ,  Peng-Fei Chuang ,  Khun Ban ,  Christopher B. Wilkerson ,  Shih-Lien L. Lu ,  Kingsum Chow

IPC分类号： G06F12/08 ,  G11C11/406

CPC分类号： G06F12/0862 ,  G06F8/4442 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/602 ,  Y02D10/13

摘要： In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括具有一个或多个执行单元的至少一个核，第一高速缓冲存储器和第一高速缓存控制逻辑。 第一高速缓存控制逻辑可以被配置为生成预取第一数据的第一预取请求，其中如果第一数据不存在于耦合到第一高速缓存存储器的第二高速缓冲存储器中，则该请求将被中止。 描述和要求保护其他实施例。

公开(公告)号：US09001608B1

公开(公告)日：2015-04-07

申请号：US14099621

申请日：2013-12-06

申请人： Zeshan A. Chishti ,  Ishwar Bhati

发明人： Zeshan A. Chishti ,  Ishwar Bhati

IPC分类号： G11C7/00 ,  G11C11/406

CPC分类号： G11C11/40611 ,  G11C2211/4061

摘要： Provided are a memory system, device, and method for determining to send a refresh command to a memory module according to a refresh rate and incrementing a postponed refresh count while the memory module is in an active mode in response to the determining to send the refresh command. The refresh command is not sent to the memory module when the postponed refresh count is incremented. A determination is made as to whether the postponed refresh count exceeds a count threshold. A refresh command is issued to the memory module to perform refresh in an active mode in response to determining that the postponed refresh count exceeds the count threshold.

摘要翻译： 提供了一种存储器系统，设备和方法，用于响应于确定发送刷新而确定在存储器模块处于活动模式的同时根据刷新速率向存储器模块发送刷新命令并递增推迟的刷新计数 命令。 当推迟刷新计数增加时，刷新命令不会发送到内存模块。 确定推迟的刷新计数是否超过计数阈值。 响应于确定推迟的刷新计数超过计数阈值，向存储器模块发出刷新命令以在活动模式下执行刷新。

公开(公告)号：US08806285B2

公开(公告)日：2014-08-12

申请号：US13485474

申请日：2012-05-31

申请人： Alaa R. Alameldeen ,  Ilya Wagner ,  Zeshan A. Chishti ,  Wei Wu ,  Christopher B. Wilkerson

发明人： Alaa R. Alameldeen ,  Ilya Wagner ,  Zeshan A. Chishti ,  Wei Wu ,  Christopher B. Wilkerson

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G06F11/27 ,  G06F11/1048 ,  G06F11/2205

摘要： Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The system deactivates and tests the second group of memory units for errors. In response to detecting an error in a memory unit of the second group, the system applies, to the memory unit of the second group having the error, the error mitigation mechanism for active use. The system then activates the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.

摘要翻译： 实施例包括动态可分配的存储器错误缓解的方法和系统。 在一个实施例中，系统将错误缓解机制应用于多组存储器单元中的一组，其中在第二组存储器单元的错误测试期间，一组正在使用。 系统停用并测试第二组存储器单元的错误。 响应于检测到第二组的存储器单元中的错误，系统向具有错误的第二组的存储器单元应用用于主动使用的错误减轻机制。 然后，该系统激活第二组存储器单元，其中将误差减轻机制应用于具有该错误的第二组的存储器单元。